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https://github.com/open-goal/jak-project.git
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c8d382b35c
* xmm spill * improve getting stack variables * improve symbol getting * update changelog
901 lines
28 KiB
C++
901 lines
28 KiB
C++
/*!
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* @file Allocator.cpp
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* Implementation of register allocation algorithms
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*/
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#include <algorithm>
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#include "third-party/fmt/core.h"
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#include "Allocator.h"
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/*!
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* Find basic blocks and add block link info.
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*/
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void find_basic_blocks(RegAllocCache* cache, const AllocationInput& in) {
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std::vector<int> dividers;
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dividers.push_back(0);
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dividers.push_back(in.instructions.size());
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// loop over instructions, finding jump targets
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for (uint32_t i = 0; i < in.instructions.size(); i++) {
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const auto& instr = in.instructions[i];
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if (!instr.jumps.empty()) {
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dividers.push_back(i + 1);
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for (auto dest : instr.jumps) {
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dividers.push_back(dest);
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}
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}
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}
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// sort dividers, and make blocks
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std::sort(dividers.begin(), dividers.end(), [](int a, int b) { return a < b; });
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for (uint32_t i = 0; i < dividers.size() - 1; i++) {
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if (dividers[i] != dividers[i + 1]) {
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// new basic block!
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RegAllocBasicBlock block;
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for (int j = dividers[i]; j < dividers[i + 1]; j++) {
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block.instr_idx.push_back(j);
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}
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block.idx = cache->basic_blocks.size();
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cache->basic_blocks.push_back(block);
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}
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}
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if (!cache->basic_blocks.empty()) {
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cache->basic_blocks.front().is_entry = true;
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cache->basic_blocks.back().is_exit = true;
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}
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auto find_basic_block_to_target = [&](int instr) {
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bool found = false;
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uint32_t result = -1;
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for (uint32_t i = 0; i < cache->basic_blocks.size(); i++) {
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if (!cache->basic_blocks[i].instr_idx.empty() &&
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cache->basic_blocks[i].instr_idx.front() == instr) {
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assert(!found);
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found = true;
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result = i;
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}
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}
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if (!found) {
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printf("[RegAlloc Error] couldn't find basic block beginning with instr %d of %d\n", instr,
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int(in.instructions.size()));
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}
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assert(found);
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return result;
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};
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// link blocks
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for (auto& block : cache->basic_blocks) {
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assert(!block.instr_idx.empty());
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auto& last_instr = in.instructions.at(block.instr_idx.back());
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if (last_instr.fallthrough) {
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// try to link to next block:
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int next_idx = block.idx + 1;
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if (next_idx < (int)cache->basic_blocks.size()) {
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cache->basic_blocks.at(next_idx).pred.push_back(block.idx);
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block.succ.push_back(next_idx);
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}
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}
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for (auto target : last_instr.jumps) {
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cache->basic_blocks.at(find_basic_block_to_target(target)).pred.push_back(block.idx);
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block.succ.push_back(find_basic_block_to_target(target));
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}
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}
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}
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namespace {
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/*!
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* Setup live_ranges. Must have found where iregs are live first.
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*/
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void compute_live_ranges(RegAllocCache* cache, const AllocationInput& in) {
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// then resize live ranges to the correct size
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cache->live_ranges.resize(cache->max_var, LiveInfo(in.instructions.size(), 0));
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// now compute the ranges
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for (auto& block : cache->basic_blocks) {
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// from var use
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for (auto instr_id : block.instr_idx) {
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auto& inst = in.instructions.at(instr_id);
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for (auto& lst : {inst.read, inst.write}) {
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for (auto& x : lst) {
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cache->live_ranges.at(x.id).add_live_instruction(instr_id);
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}
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}
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}
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// and liveliness analysis
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assert(block.live.size() == block.instr_idx.size());
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for (uint32_t i = 0; i < block.live.size(); i++) {
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for (int j = 0; j < block.live[i].size(); j++) {
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if (block.live[i][j]) {
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cache->live_ranges.at(j).add_live_instruction(block.instr_idx.at(i));
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}
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}
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}
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}
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// make us alive at any constrained instruction. todo, if this happens is this a sign of an issue
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for (auto& con : in.constraints) {
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if (!con.contrain_everywhere) {
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cache->live_ranges.at(con.ireg.id).add_live_instruction(con.instr_idx);
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}
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}
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}
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} // namespace
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/*!
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* Analysis pass to find out where registers are live. Must have found basic blocks first.
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*/
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void analyze_liveliness(RegAllocCache* cache, const AllocationInput& in) {
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cache->max_var = in.max_vars;
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cache->was_colored.resize(cache->max_var, false);
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cache->iregs.resize(cache->max_var);
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for (auto& instr : in.instructions) {
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for (auto& wr : instr.write) {
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cache->iregs.at(wr.id) = wr;
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}
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for (auto& rd : instr.read) {
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cache->iregs.at(rd.id) = rd;
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}
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}
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// phase 1
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for (auto& block : cache->basic_blocks) {
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block.live.resize(block.instr_idx.size());
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block.dead.resize(block.instr_idx.size());
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block.analyze_liveliness_phase1(in.instructions);
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}
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// phase 2
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bool changed = false;
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do {
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changed = false;
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for (auto& block : cache->basic_blocks) {
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if (block.analyze_liveliness_phase2(cache->basic_blocks, in.instructions)) {
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changed = true;
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}
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}
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} while (changed);
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// phase 3
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for (auto& block : cache->basic_blocks) {
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block.analyze_liveliness_phase3(cache->basic_blocks, in.instructions);
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}
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// phase 4
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compute_live_ranges(cache, in);
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// final setup!
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for (size_t i = 0; i < cache->live_ranges.size(); i++) {
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cache->live_ranges.at(i).prepare_for_allocation(i);
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}
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cache->stack_ops.resize(in.instructions.size());
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// cache a list of live ranges which are live at each instruction.
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// filters out unseen lr's as well.
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// this makes instr * lr1 * lr2 loop much faster!
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cache->live_ranges_by_instr.resize(in.instructions.size());
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for (u32 lr_idx = 0; lr_idx < cache->live_ranges.size(); lr_idx++) {
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auto& lr = cache->live_ranges.at(lr_idx);
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if (lr.seen) {
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for (int i = lr.min; i <= lr.max; i++) {
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if (lr.is_live_at_instr(i)) {
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cache->live_ranges_by_instr.at(i).push_back(lr_idx);
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}
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}
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}
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}
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}
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void RegAllocBasicBlock::analyze_liveliness_phase1(const std::vector<RegAllocInstr>& instructions) {
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for (int i = instr_idx.size(); i-- > 0;) {
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auto ii = instr_idx.at(i);
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auto& instr = instructions.at(ii);
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auto& lv = live.at(i);
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auto& dd = dead.at(i);
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// make all read live out
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lv.clear();
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for (auto& x : instr.read) {
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lv.insert(x.id);
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}
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// kill things which are overwritten
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dd.clear();
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for (auto& x : instr.write) {
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if (!lv[x.id]) {
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dd.insert(x.id);
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}
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}
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use.bitwise_and_not(dd);
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use.bitwise_or(lv);
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defs.bitwise_and_not(lv);
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defs.bitwise_or(dd);
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}
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}
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bool RegAllocBasicBlock::analyze_liveliness_phase2(std::vector<RegAllocBasicBlock>& blocks,
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const std::vector<RegAllocInstr>& instructions) {
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(void)instructions;
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bool changed = false;
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auto out = defs;
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for (auto s : succ) {
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out.bitwise_or(blocks.at(s).input);
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}
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IRegSet in = use;
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IRegSet temp = out;
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temp.bitwise_and_not(defs);
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in.bitwise_or(temp);
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if (in != input || out != output) {
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changed = true;
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input = in;
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output = out;
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}
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return changed;
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}
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void RegAllocBasicBlock::analyze_liveliness_phase3(std::vector<RegAllocBasicBlock>& blocks,
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const std::vector<RegAllocInstr>& instructions) {
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(void)instructions;
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IRegSet live_local;
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for (auto s : succ) {
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live_local.bitwise_or(blocks.at(s).input);
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}
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for (int i = instr_idx.size(); i-- > 0;) {
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auto& lv = live.at(i);
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auto& dd = dead.at(i);
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IRegSet new_live = live_local;
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new_live.bitwise_and_not(dd);
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new_live.bitwise_or(lv);
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lv = live_local;
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live_local = new_live;
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}
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}
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std::string RegAllocBasicBlock::print_summary() {
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std::string result = "block " + std::to_string(idx) + "\nsucc: ";
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for (auto s : succ) {
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result += std::to_string(s) + " ";
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}
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result += "\npred: ";
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for (auto p : pred) {
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result += std::to_string(p) + " ";
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}
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result += "\nuse: ";
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for (int x = 0; x < use.size(); x++) {
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if (use[x]) {
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result += std::to_string(x) + " ";
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}
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}
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result += "\ndef: ";
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for (int x = 0; x < defs.size(); x++) {
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if (defs[x]) {
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result += std::to_string(x) + " ";
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}
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}
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result += "\ninput: ";
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for (int x = 0; x < input.size(); x++) {
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if (input[x]) {
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result += std::to_string(x) + " ";
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}
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}
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result += "\noutput: ";
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for (int x = 0; x < output.size(); x++) {
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if (output[x]) {
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result += std::to_string(x) + " ";
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}
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}
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return result;
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}
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std::string RegAllocBasicBlock::print(const std::vector<RegAllocInstr>& insts) {
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std::string result = print_summary() + "\n";
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int k = 0;
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for (auto instr : instr_idx) {
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std::string line = insts.at(instr).print();
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constexpr int pad_len = 30;
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if (line.length() < pad_len) {
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// line.insert(line.begin(), pad_len - line.length(), ' ');
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line.append(pad_len - line.length(), ' ');
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}
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result += " " + line + " live: ";
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for (int x = 0; x < live.at(k).size(); x++) {
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if (live.at(k)[x]) {
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result += std::to_string(x) + " ";
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}
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}
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result += "\n";
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k++;
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}
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return result;
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}
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/*!
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* Assign registers which are constrained. If constraints are inconsistent, won't succeed in
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* satisfying them (of course), and won't error either. Use check_constrained_alloc to confirm
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* that all constraints are then satisfied.
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*/
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void do_constrained_alloc(RegAllocCache* cache, const AllocationInput& in, bool trace_debug) {
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for (auto& constr : in.constraints) {
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auto var_id = constr.ireg.id;
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if (trace_debug) {
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fmt::print("[RA] Apply constraint {}\n", constr.to_string());
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}
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if (constr.contrain_everywhere) {
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cache->live_ranges.at(var_id).constrain_everywhere(constr.desired_register);
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} else {
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cache->live_ranges.at(var_id).constrain_at_one(constr.instr_idx, constr.desired_register);
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}
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}
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}
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/*!
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* Check to run after do_constrained_alloc to see if the constraints could actually be satisfied.
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*/
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bool check_constrained_alloc(RegAllocCache* cache, const AllocationInput& in) {
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bool ok = true;
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for (auto& constr : in.constraints) {
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if (constr.contrain_everywhere) {
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auto& lr = cache->live_ranges.at(constr.ireg.id);
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for (int i = lr.min; i <= lr.max; i++) {
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if (!lr.conflicts_at(i, constr.desired_register)) {
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fmt::print("[RegAlloc Error] There are conflicting constraints on {}: {} and {}\n",
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constr.ireg.to_string(), constr.desired_register.print(),
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cache->live_ranges.at(constr.ireg.id).get(i).to_string());
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ok = false;
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}
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}
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} else {
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if (!cache->live_ranges.at(constr.ireg.id)
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.conflicts_at(constr.instr_idx, constr.desired_register)) {
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fmt::print("[RegAlloc Error] There are conflicting constraints on {}: {} and {}\n",
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constr.ireg.to_string(), constr.desired_register.print(),
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cache->live_ranges.at(constr.ireg.id).get(constr.instr_idx).to_string());
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ok = false;
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}
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}
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}
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for (uint32_t i = 0; i < in.instructions.size(); i++) {
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for (auto idx1 : cache->live_ranges_by_instr.at(i)) {
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auto& lr1 = cache->live_ranges.at(idx1);
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for (auto idx2 : cache->live_ranges_by_instr.at(i)) {
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if (idx1 == idx2) {
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continue;
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}
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auto& lr2 = cache->live_ranges.at(idx2);
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// if lr1 is assigned...
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auto& ass1 = lr1.get(i);
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if (ass1.kind != Assignment::Kind::UNASSIGNED) {
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auto& ass2 = lr2.get(i);
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if (ass1.occupies_same_reg(ass2)) {
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// todo, this error won't be helpful
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fmt::print(
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"[RegAlloc Error] Cannot satisfy constraints at instruction {} due to constraints "
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"on {} and {}\n",
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i, lr1.var, lr2.var);
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ok = false;
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}
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}
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}
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}
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}
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return ok;
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}
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namespace {
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/*!
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* Assign variable to register. Don't check if its safe. If it's already assigned, and this would
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* change that assignment, throw.
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*/
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void assign_var_no_check(int var, Assignment ass, RegAllocCache* cache) {
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cache->live_ranges.at(var).assign_no_overwrite(ass);
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}
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/*!
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* Can var be assigned to ass?
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*/
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bool can_var_be_assigned(int var,
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Assignment ass,
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RegAllocCache* cache,
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const AllocationInput& in,
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int debug_trace) {
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// our live range:
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auto& lr = cache->live_ranges.at(var);
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// check against all other live ranges:
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for (int instr = lr.min; instr <= lr.max; instr++) {
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for (int other_idx : cache->live_ranges_by_instr.at(instr)) {
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auto& other_lr = cache->live_ranges.at(other_idx);
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if (other_lr.var == var) {
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continue;
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}
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// LR's overlap
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if (/*(instr != other_lr.max) && */ other_lr.conflicts_at(instr, ass)) {
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bool allowed_by_move_eliminator = false;
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if (move_eliminator) {
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if (enable_fancy_coloring) {
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if (lr.dies_next_at_instr(instr) && other_lr.becomes_live_at_instr(instr) &&
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(allow_read_write_same_reg || in.instructions.at(instr).is_move)) {
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allowed_by_move_eliminator = true;
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}
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if (lr.becomes_live_at_instr(instr) && other_lr.dies_next_at_instr(instr) &&
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(allow_read_write_same_reg || in.instructions.at(instr).is_move)) {
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allowed_by_move_eliminator = true;
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}
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} else {
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// case to allow rename (from us to them)
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if (instr == lr.max && instr == other_lr.min && in.instructions.at(instr).is_move) {
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allowed_by_move_eliminator = true;
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}
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if (instr == lr.min && instr == other_lr.min && in.instructions.at(instr).is_move) {
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allowed_by_move_eliminator = true;
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}
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}
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}
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if (!allowed_by_move_eliminator) {
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if (debug_trace >= 1) {
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printf("at idx %d, %s conflicts\n", instr, other_lr.print_assignment().c_str());
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}
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return false;
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}
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}
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}
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}
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// can clobber on the last one or first one - check that we don't interfere with a clobber
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for (int instr = lr.min + 1; instr <= lr.max - 1; instr++) {
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for (auto clobber : in.instructions.at(instr).clobber) {
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if (ass.occupies_reg(clobber)) {
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if (debug_trace >= 1) {
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printf("at idx %d clobber\n", instr);
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}
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return false;
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}
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}
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}
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for (int instr = lr.min; instr <= lr.max; instr++) {
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for (auto exclusive : in.instructions.at(instr).exclude) {
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if (ass.occupies_reg(exclusive)) {
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if (debug_trace >= 1) {
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printf("at idx %d exclusive conflict\n", instr);
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}
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return false;
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}
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}
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}
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// check we don't violate any others.
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for (int instr = lr.min; instr <= lr.max; instr++) {
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if (lr.has_constraint && lr.assignment.at(instr - lr.min).is_assigned()) {
|
|
if (!(ass.occupies_same_reg(lr.assignment.at(instr - lr.min)))) {
|
|
if (debug_trace >= 1) {
|
|
printf("at idx %d self bad (%s) (%s)\n", instr,
|
|
lr.assignment.at(instr - lr.min).to_string().c_str(), ass.to_string().c_str());
|
|
}
|
|
|
|
return false;
|
|
}
|
|
}
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
bool assignment_ok_at(int var,
|
|
int idx,
|
|
Assignment ass,
|
|
RegAllocCache* cache,
|
|
const AllocationInput& in,
|
|
int debug_trace) {
|
|
auto& lr = cache->live_ranges.at(var);
|
|
for (auto other_idx : cache->live_ranges_by_instr.at(idx)) {
|
|
auto& other_lr = cache->live_ranges.at(other_idx);
|
|
if (other_lr.var == var) {
|
|
continue;
|
|
}
|
|
|
|
if (/*(idx != other_lr.max) &&*/ other_lr.conflicts_at(idx, ass)) {
|
|
bool allowed_by_move_eliminator = false;
|
|
if (move_eliminator) {
|
|
if (enable_fancy_coloring) {
|
|
if (lr.dies_next_at_instr(idx) && other_lr.becomes_live_at_instr(idx) &&
|
|
(allow_read_write_same_reg || in.instructions.at(idx).is_move)) {
|
|
allowed_by_move_eliminator = true;
|
|
}
|
|
|
|
if (lr.becomes_live_at_instr(idx) && other_lr.dies_next_at_instr(idx) &&
|
|
(allow_read_write_same_reg || in.instructions.at(idx).is_move)) {
|
|
allowed_by_move_eliminator = true;
|
|
}
|
|
} else {
|
|
// case to allow rename (from us to them)
|
|
if (idx == lr.max && idx == other_lr.min && in.instructions.at(idx).is_move) {
|
|
allowed_by_move_eliminator = true;
|
|
}
|
|
|
|
if (idx == lr.min && idx == other_lr.min && in.instructions.at(idx).is_move) {
|
|
allowed_by_move_eliminator = true;
|
|
}
|
|
}
|
|
}
|
|
|
|
if (!allowed_by_move_eliminator) {
|
|
if (debug_trace >= 2) {
|
|
printf("at idx %d, %s conflicts\n", idx, other_lr.print_assignment().c_str());
|
|
}
|
|
return false;
|
|
}
|
|
}
|
|
}
|
|
|
|
// check we aren't violating a clobber
|
|
if (idx != lr.min && idx != lr.max) {
|
|
for (auto clobber : in.instructions.at(idx).clobber) {
|
|
if (ass.occupies_reg(clobber)) {
|
|
if (debug_trace >= 2) {
|
|
printf("at idx %d clobber\n", idx);
|
|
}
|
|
|
|
return false;
|
|
}
|
|
}
|
|
}
|
|
|
|
for (auto exclusive : in.instructions.at(idx).exclude) {
|
|
if (ass.occupies_reg(exclusive)) {
|
|
if (debug_trace >= 2) {
|
|
printf("at idx %d exclusive conflict\n", idx);
|
|
}
|
|
|
|
return false;
|
|
}
|
|
}
|
|
|
|
// check we aren't violating ourselves
|
|
if (lr.assignment.at(idx - lr.min).is_assigned()) {
|
|
if (!(ass.occupies_same_reg(lr.assignment.at(idx - lr.min)))) {
|
|
if (debug_trace >= 2) {
|
|
printf("at idx %d self bad\n", idx);
|
|
}
|
|
|
|
return false;
|
|
}
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
bool try_assignment_for_var(int var,
|
|
Assignment ass,
|
|
RegAllocCache* cache,
|
|
const AllocationInput& in,
|
|
int debug_trace) {
|
|
if (can_var_be_assigned(var, ass, cache, in, debug_trace)) {
|
|
assign_var_no_check(var, ass, cache);
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
int get_stack_slot_for_var(int var, RegAllocCache* cache) {
|
|
auto kv = cache->var_to_stack_slot.find(var);
|
|
if (kv == cache->var_to_stack_slot.end()) {
|
|
auto slot = cache->current_stack_slot++;
|
|
cache->var_to_stack_slot[var] = slot;
|
|
return slot;
|
|
} else {
|
|
return kv->second;
|
|
}
|
|
}
|
|
|
|
const std::vector<emitter::Register>& get_default_alloc_order_for_var_spill(int v,
|
|
RegAllocCache* cache) {
|
|
auto& info = cache->iregs.at(v);
|
|
assert(info.reg_class != RegClass::INVALID);
|
|
auto hw_kind = emitter::reg_class_to_hw(info.reg_class);
|
|
if (hw_kind == emitter::HWRegKind::GPR) {
|
|
return emitter::gRegInfo.get_gpr_spill_alloc_order();
|
|
} else if (hw_kind == emitter::HWRegKind::XMM) {
|
|
return emitter::gRegInfo.get_xmm_spill_alloc_order();
|
|
} else {
|
|
throw std::runtime_error("Unsupported HWRegKind");
|
|
}
|
|
}
|
|
|
|
const std::vector<emitter::Register>& get_default_alloc_order_for_var(int v,
|
|
RegAllocCache* cache,
|
|
bool get_all) {
|
|
auto& info = cache->iregs.at(v);
|
|
assert(info.reg_class != RegClass::INVALID);
|
|
auto hw_kind = emitter::reg_class_to_hw(info.reg_class);
|
|
if (hw_kind == emitter::HWRegKind::GPR || hw_kind == emitter::HWRegKind::INVALID) {
|
|
if (!get_all && cache->is_asm_func) {
|
|
return emitter::gRegInfo.get_gpr_temp_alloc_order();
|
|
} else {
|
|
return emitter::gRegInfo.get_gpr_alloc_order();
|
|
}
|
|
} else if (hw_kind == emitter::HWRegKind::XMM) {
|
|
if (!get_all && cache->is_asm_func) {
|
|
return emitter::gRegInfo.get_xmm_temp_alloc_order();
|
|
} else {
|
|
return emitter::gRegInfo.get_xmm_alloc_order();
|
|
}
|
|
} else {
|
|
throw std::runtime_error("Unsupported HWRegKind");
|
|
}
|
|
}
|
|
|
|
bool try_spill_coloring(int var, RegAllocCache* cache, const AllocationInput& in, int debug_trace) {
|
|
// todo, reject flagged "unspillables"
|
|
if (debug_trace >= 1) {
|
|
printf("---- SPILL VAR %d ----\n", var);
|
|
}
|
|
|
|
auto& lr = cache->live_ranges.at(var);
|
|
|
|
// possibly get a hint assignment
|
|
Assignment hint_assignment;
|
|
hint_assignment.kind = Assignment::Kind::UNASSIGNED;
|
|
|
|
// loop over live range
|
|
for (int instr = lr.min; instr <= lr.max; instr++) {
|
|
// bonus_instructions.at(instr).clear();
|
|
StackOp::Op bonus;
|
|
bonus.reg_class = cache->iregs.at(var).reg_class;
|
|
|
|
// we may have a constaint in here
|
|
auto& current_assignment = lr.assignment.at(instr - lr.min);
|
|
|
|
auto& op = in.instructions.at(instr);
|
|
bool is_read = op.reads(var);
|
|
bool is_written = op.writes(var);
|
|
|
|
// we have a constraint!
|
|
if (current_assignment.is_assigned()) {
|
|
if (debug_trace >= 2) {
|
|
printf(" [%02d] already assigned %s\n", instr, current_assignment.to_string().c_str());
|
|
}
|
|
|
|
// remember this assignment as a hint for later
|
|
hint_assignment = current_assignment;
|
|
// check that this assignment is ok
|
|
if (!assignment_ok_at(var, instr, current_assignment, cache, in, debug_trace)) {
|
|
// this shouldn't be possible with feasible constraints
|
|
printf("-- SPILL FAILED -- IMPOSSIBLE CONSTRAINT @ %d %s. This is likely a RegAlloc bug!\n",
|
|
instr, current_assignment.to_string().c_str());
|
|
assert(false);
|
|
return false;
|
|
}
|
|
|
|
// flag it as spilled, but currently in a GPR.
|
|
current_assignment.spilled = true;
|
|
bonus.reg = current_assignment.reg;
|
|
} else {
|
|
// not assigned.
|
|
if (debug_trace >= 1) {
|
|
printf(" [%02d] nya rd? %d wr? %d\n", instr, is_read, is_written);
|
|
}
|
|
|
|
// We'd like to keep it on the stack if possible
|
|
Assignment spill_assignment;
|
|
spill_assignment.spilled = true;
|
|
spill_assignment.kind = Assignment::Kind::STACK;
|
|
spill_assignment.reg = -1; // for now
|
|
|
|
// needs a temp register
|
|
if (is_read || is_written) {
|
|
// we need to put it in a register here!
|
|
// first check if the hint works?
|
|
// todo floats?
|
|
if (hint_assignment.kind == Assignment::Kind::REGISTER) {
|
|
if (debug_trace >= 2) {
|
|
printf(" try hint %s\n", hint_assignment.to_string().c_str());
|
|
}
|
|
|
|
if (assignment_ok_at(var, instr, hint_assignment, cache, in, debug_trace)) {
|
|
// it's ok!
|
|
if (debug_trace >= 2) {
|
|
printf(" it worked!\n");
|
|
}
|
|
spill_assignment.reg = hint_assignment.reg;
|
|
}
|
|
}
|
|
|
|
// hint didn't work
|
|
// auto reg_order = get_default_reg_alloc_order();
|
|
auto reg_order = get_default_alloc_order_for_var_spill(var, cache);
|
|
if (spill_assignment.reg == -1) {
|
|
for (auto reg : reg_order) {
|
|
Assignment ass;
|
|
ass.kind = Assignment::Kind::REGISTER;
|
|
ass.reg = reg;
|
|
if (debug_trace >= 2) {
|
|
printf(" try %s\n", ass.to_string().c_str());
|
|
}
|
|
|
|
if (assignment_ok_at(var, instr, ass, cache, in, debug_trace)) {
|
|
if (debug_trace >= 2) {
|
|
printf(" it worked!\n");
|
|
}
|
|
spill_assignment.reg = ass.reg;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
if (spill_assignment.reg == -1) {
|
|
printf("SPILLING FAILED BECAUSE WE COULDN'T FIND A TEMP REGISTER!\n");
|
|
assert(false);
|
|
// std::vector<bool> can_try_spilling;
|
|
// for(uint32_t other_spill = 0; other_spill < was_colored.size(); other_spill++)
|
|
// {
|
|
// if((int)other_spill != var && was_colored.at(other_spill)) {
|
|
// LOG("TRY SPILL %d?\n", other_spill);
|
|
// if(try_spill_coloring(other_spill)) {
|
|
// LOG("SPILL OK.\n");
|
|
// if(try_spill_coloring(var)) {
|
|
// return true;
|
|
// }
|
|
// } else {
|
|
// LOG("SPILL %d failed.\n", other_spill);
|
|
// }
|
|
// }
|
|
// }
|
|
return false;
|
|
}
|
|
|
|
// mark that it's in a GPR!
|
|
spill_assignment.kind = Assignment::Kind::REGISTER;
|
|
} // end need temp reg
|
|
spill_assignment.stack_slot = get_stack_slot_for_var(var, cache);
|
|
lr.assignment.at(instr - lr.min) = spill_assignment;
|
|
bonus.reg = spill_assignment.reg;
|
|
bonus.slot = spill_assignment.stack_slot;
|
|
} // end not constrained
|
|
|
|
bonus.slot = get_stack_slot_for_var(var, cache);
|
|
bonus.load = is_read;
|
|
bonus.store = is_written;
|
|
|
|
if (bonus.load || bonus.store) {
|
|
cache->stack_ops.at(instr).ops.push_back(bonus);
|
|
}
|
|
}
|
|
return true;
|
|
}
|
|
|
|
template <typename T>
|
|
bool in_vec(const std::vector<T>& vec, const T& obj) {
|
|
for (const auto& x : vec) {
|
|
if (x == obj)
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
bool do_allocation_for_var(int var,
|
|
RegAllocCache* cache,
|
|
const AllocationInput& in,
|
|
int debug_trace) {
|
|
// first, let's see if there's a hint...
|
|
auto& lr = cache->live_ranges.at(var);
|
|
bool colored = false;
|
|
if (lr.best_hint.is_assigned()) {
|
|
colored = try_assignment_for_var(var, lr.best_hint, cache, in, debug_trace);
|
|
if (debug_trace >= 2) {
|
|
printf("var %d reg %s ? %d\n", var, lr.best_hint.to_string().c_str(), colored);
|
|
}
|
|
}
|
|
|
|
auto reg_order = get_default_alloc_order_for_var(var, cache, false);
|
|
auto& all_reg_order = get_default_alloc_order_for_var(var, cache, true);
|
|
|
|
// todo, try other regs..
|
|
if (!colored && move_eliminator) {
|
|
auto& first_instr = in.instructions.at(lr.min);
|
|
auto& last_instr = in.instructions.at(lr.max);
|
|
|
|
if (!colored && last_instr.is_move) {
|
|
auto& possible_coloring = cache->live_ranges.at(last_instr.write.front().id).get(lr.max);
|
|
if (possible_coloring.is_assigned() && in_vec(all_reg_order, possible_coloring.reg)) {
|
|
colored = try_assignment_for_var(var, possible_coloring, cache, in, debug_trace);
|
|
}
|
|
}
|
|
|
|
if (!colored && first_instr.is_move) {
|
|
auto& possible_coloring = cache->live_ranges.at(first_instr.read.front().id).get(lr.min);
|
|
if (possible_coloring.is_assigned() && in_vec(all_reg_order, possible_coloring.reg)) {
|
|
colored = try_assignment_for_var(var, possible_coloring, cache, in, debug_trace);
|
|
}
|
|
}
|
|
}
|
|
|
|
// auto reg_order = get_default_reg_alloc_order();
|
|
|
|
for (auto reg : reg_order) {
|
|
if (colored)
|
|
break;
|
|
Assignment ass;
|
|
ass.kind = Assignment::Kind::REGISTER;
|
|
ass.reg = reg;
|
|
colored = try_assignment_for_var(var, ass, cache, in, debug_trace);
|
|
if (debug_trace >= 1) {
|
|
printf("var %d reg %s ? %d\n", var, ass.to_string().c_str(), colored);
|
|
}
|
|
}
|
|
|
|
if (!colored) {
|
|
colored = try_spill_coloring(var, cache, in, debug_trace);
|
|
if (colored) {
|
|
cache->used_stack = true;
|
|
}
|
|
}
|
|
|
|
// todo, try spilling
|
|
if (!colored) {
|
|
printf("[ERROR] var %d could not be colored:\n%s\n", var,
|
|
cache->live_ranges.at(var).print_assignment().c_str());
|
|
|
|
return false;
|
|
} else {
|
|
if (debug_trace >= 2) {
|
|
printf("Colored var %d\n", var);
|
|
}
|
|
|
|
cache->was_colored.at(var) = true;
|
|
return true;
|
|
}
|
|
}
|
|
|
|
} // namespace
|
|
|
|
bool run_allocator(RegAllocCache* cache, const AllocationInput& in, int debug_trace) {
|
|
// here we allocate
|
|
std::vector<int> allocation_order;
|
|
for (uint32_t i = 0; i < cache->live_ranges.size(); i++) {
|
|
if (cache->live_ranges.at(i).seen && cache->live_ranges.at(i).has_constraint) {
|
|
allocation_order.push_back(i);
|
|
}
|
|
}
|
|
|
|
for (uint32_t i = 0; i < cache->live_ranges.size(); i++) {
|
|
if (cache->live_ranges.at(i).seen && !cache->live_ranges.at(i).has_constraint) {
|
|
allocation_order.push_back(i);
|
|
}
|
|
}
|
|
|
|
for (int var : allocation_order) {
|
|
if (!do_allocation_for_var(var, cache, in, debug_trace)) {
|
|
return false;
|
|
}
|
|
}
|
|
return true;
|
|
}
|