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* docs: documentation pass * docs: main README pass
327 lines
5.6 KiB
NASM
327 lines
5.6 KiB
NASM
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; .function sp-init-fields!
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;BAD PROLOGUE
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;; Warnings:
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;; INFO: Flagged as asm by config
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;; INFO: Assembly Function
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# inputs: a0 output-data (multiple types)
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# a1 init-spec-array
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# a2 start-field-idx
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# a3 end-field-idx (not inclusive, not that it matters?)
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# t0 usually #f.
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## Initialize
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B0:
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L155:
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or v1, a0, r0
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or v1, a2, r0
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or v1, a3, r0
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or v1, t0, r0
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sll r0, r0, 0
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daddiu a2, a2, 1 # actual first field to care about.
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or v0, a1, r0 # v0 = current field?
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## Loop to advance our init spec until we hit a field >= our minimum
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B1:
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L156:
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lh a1, 0(v0) # a1 = field-id
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sll r0, r0, 0
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dsubu a1, a1, a2 #
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sll r0, r0, 0
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sll r0, r0, 0
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sll r0, r0, 0
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bltzl a1, L156
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B2:
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daddiu v0, v0, 16
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## If our range is size 0 (or negative), exit early, we have no fields to initialize
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B3:
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dsubu a1, a2, a3
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sll r0, r0, 0
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bgez a1, L169
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sll r0, r0, 0
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# LOOP TOP:
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# v0 = init-spec, a2 = field to init,
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B4:
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L157:
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lh a1, 0(v0)
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sll r0, r0, 0
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bne a1, a2, L167 # jump to end if field doesn't match spec.
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vrget.xyzw vf1
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B5:
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vsqrt Q, vf1.x
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lh a1, 2(v0) # a1 = flags
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vaddq.x vf2, vf0, Q # more random?
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lw t2, 8(v0) # t2 = random-range (float or int possible here)
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addiu v1, r0, 7
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beq a2, v1, L159 # spt-sound
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addiu t1, r0, 1
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B6:
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beq a1, t1, L160 # flags = 1.
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addiu t1, r0, 2
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B7:
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beq a1, t1, L162 # flags = 2.
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addiu t1, r0, 3
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B8:
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beq a1, t1, L163 # flags = 3
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addiu t1, r0, 5
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B9:
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beq a1, t1, L164 # flags = 5
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addiu t1, r0, 6
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B10:
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beq a1, t1, L165 # flags = 6
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addiu t1, r0, 4
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B11:
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beq a1, t1, L166 # flags = 4
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sll r0, r0, 0
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B12:
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beq t2, r0, L158 # flags = 0
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sll r0, r0, 0
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B13:
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vrxorw vf2 # other flags
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lw t1, 12(v0)
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vrnext.xyzw vf1
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lw t3, 4(v0)
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vsubw.xyzw vf1, vf1, vf0
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sll r0, r0, 0
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qmtc2.i vf2, t2
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sll r0, r0, 0
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vitof0.xyzw vf2, vf2
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sll r0, r0, 0
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vmul.xyzw vf1, vf1, vf2
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sll r0, r0, 0
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vftoi0.xyzw vf1, vf1
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sll r0, r0, 0
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qmfc2.i t2, vf1
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sll r0, r0, 0
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mult3 t2, t2, t1
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sll r0, r0, 0
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daddu t2, t2, t3
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daddiu a2, a2, 1
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sw t2, 0(a0)
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daddiu a0, a0, 4
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bne a2, a3, L157
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daddiu v0, v0, 16
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B14:
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jr ra
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sll r0, r0, 0
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B15:
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L158: # flags = 0
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lw t3, 4(v0) ## int32
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daddiu a2, a2, 1
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sw t3, 0(a0)
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daddiu a0, a0, 4
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bne a2, a3, L157
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daddiu v0, v0, 16
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B16:
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jr ra
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sll r0, r0, 0
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B17:
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L159: ## special case for sound.
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lw t3, 4(v0)
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daddiu a2, a2, 1
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sw t3, 0(a0)
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daddiu a0, a0, 4
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bne a2, a3, L157
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daddiu v0, v0, 16
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B18:
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jr ra
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sll r0, r0, 0
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B19:
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L160: ## flags = 1
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beq t2, r0, L161 # skip if range = 0
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vrxorw vf2
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B20:
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vrnext.xyzw vf1
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lw t1, 12(v0) ## t1 = multiplier
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vsubw.xyzw vf1, vf1, vf0
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lw t3, 4(v0) ## t3 = initial-value
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qmtc2.i vf2, t2
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sll r0, r0, 0
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vmul.xyzw vf1, vf1, vf2
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sll r0, r0, 0
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qmtc2.i vf2, t1
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sll r0, r0, 0
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vmul.xyzw vf1, vf1, vf2
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sll r0, r0, 0
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qmtc2.i vf2, t3
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sll r0, r0, 0
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vadd.xyzw vf1, vf1, vf2
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sll r0, r0, 0
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qmfc2.i t2, vf1
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daddiu a2, a2, 1
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sw t2, 0(a0)
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daddiu a0, a0, 4
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bne a2, a3, L157
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daddiu v0, v0, 16
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B21:
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jr ra
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sll r0, r0, 0
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B22:
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L161:
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lw t3, 4(v0)
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daddiu a2, a2, 1
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sw t3, 0(a0)
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daddiu a0, a0, 4
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bne a2, a3, L157
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daddiu v0, v0, 16
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B23:
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jr ra
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sll r0, r0, 0
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B24:
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L162:
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beq t2, r0, L161 ## flags = 2
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vrxorw vf2
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B25:
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vrnext.xyzw vf1
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lw t1, 12(v0)
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vsubw.xyzw vf1, vf1, vf0
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daddiu t2, t2, 1
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qmtc2.i vf2, t2
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lw t3, 4(v0)
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vitof0.xyzw vf2, vf2
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sll r0, r0, 0
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vmul.xyzw vf1, vf1, vf2
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sll r0, r0, 0
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vftoi0.xyzw vf1, vf1
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sll r0, r0, 0
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vitof0.xyzw vf1, vf1
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sll r0, r0, 0
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qmtc2.i vf2, t1
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sll r0, r0, 0
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vmul.xyzw vf1, vf1, vf2
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sll r0, r0, 0
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qmtc2.i vf2, t3
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sll r0, r0, 0
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vadd.xyzw vf1, vf1, vf2
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sll r0, r0, 0
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qmfc2.i t2, vf1
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daddiu a2, a2, 1
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sw t2, 0(a0)
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daddiu a0, a0, 4
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bne a2, a3, L157
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daddiu v0, v0, 16
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B26:
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jr ra
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sll r0, r0, 0
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B27:
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L163: ## flags = 3
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lw t1, 4(v0) # t1 = init-val
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sll r0, r0, 0
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dsll t1, t1, 2 # val * 4
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sll r0, r0, 0
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daddu t1, t1, a0 # t1 = dest + val*4
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sll r0, r0, 0
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lw t3, 0(t1)
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daddiu a2, a2, 1
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sw t3, 0(a0)
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daddiu a0, a0, 4
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bne a2, a3, L157
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daddiu v0, v0, 16
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B28:
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jr ra
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sll r0, r0, 0
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B29:
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L164: ## flags = 5
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lw t1, 4(v0)
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sll r0, r0, 0
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lw t3, 0(t1)
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daddiu a2, a2, 1
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sw t3, 0(a0)
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daddiu a0, a0, 4
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bne a2, a3, L157
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daddiu v0, v0, 16
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B30:
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jr ra
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sll r0, r0, 0
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B31:
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L165:
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lw t1, *part-id-table*(s7) ## flags = 6
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sll r0, r0, 0
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lw t3, 4(v0)
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sll r0, r0, 0
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dsll t3, t3, 2
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daddiu t1, t1, 12
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daddu t3, t3, t1
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sll r0, r0, 0
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lw t2, 0(t3)
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daddiu a2, a2, 1
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sw t2, 0(a0)
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daddiu a0, a0, 4
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bne a2, a3, L157
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daddiu v0, v0, 16
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B32:
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jr ra
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sll r0, r0, 0
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B33:
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L166:
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lw t3, 4(v0) ## flags = 4
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daddiu a2, a2, 1
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sw t3, 0(a0)
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daddiu a0, a0, 4
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bne a2, a3, L157
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daddiu v0, v0, 16
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B34:
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jr ra
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sll r0, r0, 0
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B35:
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L167:
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bnel t0, s7, L168
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B36:
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sw r0, 0(a0)
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B37:
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L168:
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daddiu a2, a2, 1
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daddiu a0, a0, 4
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bne a2, a3, L157
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sll r0, r0, 0
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B38:
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L169:
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jr ra
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sll r0, r0, 0
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jr ra
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daddu sp, sp, r0
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sll r0, r0, 0
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sll r0, r0, 0
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sll r0, r0, 0
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