2020-09-13 21:32:55 -04:00
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#pragma once
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2020-08-29 19:13:29 -04:00
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#ifndef JAK_INSTRUCTION_H
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#define JAK_INSTRUCTION_H
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2020-08-22 22:30:12 -04:00
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#include <cassert>
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#include "common/common_types.h"
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2020-08-29 19:13:29 -04:00
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namespace emitter {
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2020-08-22 22:30:12 -04:00
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/*!
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* The ModRM byte
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*/
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struct ModRM {
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uint8_t mod;
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uint8_t reg_op;
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uint8_t rm;
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2020-08-26 01:21:33 -04:00
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uint8_t operator()() const { return (mod << 6) | (reg_op << 3) | (rm << 0); }
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2020-08-22 22:30:12 -04:00
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};
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/*!
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* The SIB Byte
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*/
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struct SIB {
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uint8_t scale, index, base;
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2020-08-26 01:21:33 -04:00
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uint8_t operator()() const { return (scale << 6) | (index << 3) | (base << 0); }
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2020-08-22 22:30:12 -04:00
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};
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/*!
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* An Immediate (either imm or disp)
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*/
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struct Imm {
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Imm() = default;
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2020-08-26 01:21:33 -04:00
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Imm(uint8_t sz, uint64_t v) : size(sz), value(v) {}
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2020-08-22 22:30:12 -04:00
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uint8_t size;
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union {
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uint64_t value;
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uint8_t v_arr[8];
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};
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};
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/*!
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* The REX prefix byte
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*/
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struct REX {
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2020-08-26 01:21:33 -04:00
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explicit REX(bool w = false, bool r = false, bool x = false, bool b = false)
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: W(w), R(r), X(x), B(b) {}
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2020-08-22 22:30:12 -04:00
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// W - 64-bit operands
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// R - reg extension
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// X - SIB i extnsion
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// B - other extension
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bool W, R, X, B;
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2020-08-26 01:21:33 -04:00
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uint8_t operator()() const { return (1 << 6) | (W << 3) | (R << 2) | (X << 1) | (B << 0); }
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2020-08-22 22:30:12 -04:00
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};
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2020-12-30 15:33:51 -05:00
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enum class VexPrefix : u8 { P_NONE = 0, P_66 = 1, P_F3 = 2, P_F2 = 3 };
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/*!
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* The "VEX" 3-byte format for AVX instructions
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*/
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struct VEX3 {
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bool W, R, X, B;
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enum class LeadingBytes : u8 { P_INVALID = 0, P_0F = 1, P_0F_38 = 2, P_0F_3A = 3 } leading_bytes;
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u8 reg_id;
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VexPrefix prefix;
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bool L;
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u8 emit(u8 byte) const {
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if (byte == 0) {
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return 0b11000100;
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} else if (byte == 1) {
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u8 result = 0;
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result |= ((!R) << 7);
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result |= ((!X) << 6);
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result |= ((!B) << 5);
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result |= (0b11111 & u8(leading_bytes));
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return result;
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} else if (byte == 2) {
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u8 result = 0;
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result |= (W << 7); // this may be inverted?
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result |= ((~reg_id) & 0b1111) << 3;
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result |= (L << 2);
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result |= (u8(prefix) & 0b11);
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return result;
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} else {
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assert(false);
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}
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}
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VEX3(bool w,
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bool r,
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bool x,
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bool b,
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LeadingBytes _leading_bytes,
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u8 _reg_id = 0,
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VexPrefix _prefix = VexPrefix::P_NONE,
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bool l = false)
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: W(w),
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R(r),
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X(x),
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B(b),
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leading_bytes(_leading_bytes),
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reg_id(_reg_id),
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prefix(_prefix),
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L(l) {}
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};
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struct VEX2 {
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bool R;
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u8 reg_id;
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VexPrefix prefix;
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bool L;
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u8 emit(u8 byte) const {
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if (byte == 0) {
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return 0b11000101;
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} else if (byte == 1) {
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u8 result = 0;
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result |= ((!R) << 7);
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result |= ((~reg_id) & 0b1111) << 3;
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result |= (L << 2);
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result |= (u8(prefix) & 0b11);
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return result;
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} else {
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assert(false);
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}
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}
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VEX2(bool r, u8 _reg_id = 0, VexPrefix _prefix = VexPrefix::P_NONE, bool l = false)
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: R(r), reg_id(_reg_id), prefix(_prefix), L(l) {}
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};
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2020-08-22 22:30:12 -04:00
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/*!
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* A high-level description of an x86-64 opcode. It can emit itself.
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*/
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struct Instruction {
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2020-08-26 01:21:33 -04:00
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Instruction(uint8_t opcode) : op(opcode) {}
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2020-08-22 22:30:12 -04:00
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uint8_t op;
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bool op2_set = false;
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uint8_t op2;
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bool op3_set = false;
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uint8_t op3;
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// if true, don't emit anything
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bool is_null = false;
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// flag to indicate it's the first instruction of a function and needs align and type tag
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bool is_function_start = false;
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2020-12-30 15:33:51 -05:00
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int n_vex = 0;
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uint8_t vex[3] = {0, 0, 0};
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2020-08-22 22:30:12 -04:00
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// the rex byte
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bool set_rex = false;
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uint8_t m_rex = 0;
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// the modrm byte
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bool set_modrm = false;
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uint8_t m_modrm = 0;
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// the sib byte
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bool set_sib = false;
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uint8_t m_sib = 0;
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// the displacement
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bool set_disp_imm = false;
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Imm disp;
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// the immediate
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bool set_imm = false;
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Imm imm;
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/*!
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* Move opcode byte 0 to before the rex prefix.
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*/
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void swap_op0_rex() {
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2020-08-26 01:21:33 -04:00
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if (!set_rex)
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return;
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2020-08-22 22:30:12 -04:00
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auto temp = op;
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op = m_rex;
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m_rex = temp;
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}
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void set(REX r) {
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m_rex = r();
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set_rex = true;
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}
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void set(ModRM modrm) {
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m_modrm = modrm();
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set_modrm = true;
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}
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void set(SIB sib) {
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m_sib = sib();
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set_sib = true;
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}
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2020-12-30 15:33:51 -05:00
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void set(VEX3 vex3) {
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n_vex = 3;
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for (int i = 0; i < n_vex; i++) {
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vex[i] = vex3.emit(i);
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}
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}
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void set(VEX2 vex2) {
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n_vex = 2;
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for (int i = 0; i < n_vex; i++) {
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vex[i] = vex2.emit(i);
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}
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}
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2020-08-22 22:30:12 -04:00
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void set_disp(Imm i) {
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disp = i;
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set_disp_imm = true;
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}
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void set(Imm i) {
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imm = i;
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set_imm = true;
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}
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void set_op2(uint8_t b) {
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op2_set = true;
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op2 = b;
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}
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void set_op3(uint8_t b) {
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op3_set = true;
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op3 = b;
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}
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2020-09-05 16:37:37 -04:00
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int get_imm_size() const {
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if (set_imm) {
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return imm.size;
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} else {
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return 0;
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}
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}
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int get_disp_size() const {
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if (set_disp_imm) {
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return disp.size;
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} else {
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return 0;
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}
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}
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2020-08-22 22:30:12 -04:00
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/*!
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* Set modrm and rex as needed for two regs.
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*/
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void set_modrm_and_rex(uint8_t reg, uint8_t rm, uint8_t mod, bool rex_w = false) {
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bool rex_b = false, rex_r = false;
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2020-08-26 01:21:33 -04:00
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if (rm >= 8) {
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2020-08-22 22:30:12 -04:00
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rm -= 8;
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rex_b = true;
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}
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2020-08-26 01:21:33 -04:00
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if (reg >= 8) {
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2020-08-22 22:30:12 -04:00
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reg -= 8;
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rex_r = true;
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}
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ModRM modrm;
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modrm.mod = mod;
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modrm.reg_op = reg;
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modrm.rm = rm;
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set(modrm);
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2020-08-26 01:21:33 -04:00
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if (rex_b || rex_w || rex_r) {
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2020-08-22 22:30:12 -04:00
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set(REX(rex_w, rex_r, false, rex_b));
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}
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}
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2020-12-30 15:33:51 -05:00
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void set_vex_modrm_and_rex(uint8_t reg,
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uint8_t rm,
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VEX3::LeadingBytes lb,
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uint8_t vex_reg = 0,
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bool rex_w = false,
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VexPrefix prefix = VexPrefix::P_NONE) {
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bool rex_b = false, rex_r = false;
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if (rm >= 8) {
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rm -= 8;
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rex_b = true;
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}
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if (reg >= 8) {
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reg -= 8;
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rex_r = true;
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}
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ModRM modrm;
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modrm.mod = 3;
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modrm.reg_op = reg;
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modrm.rm = rm;
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set(modrm);
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if (rex_b || rex_w || lb != VEX3::LeadingBytes::P_0F) {
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// need three byte version
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set(VEX3(rex_w, rex_r, false, rex_b, lb, vex_reg, prefix));
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} else {
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assert(lb == VEX3::LeadingBytes::P_0F); // vex2 implies 0x0f
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assert(!rex_b);
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assert(!rex_w);
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set(VEX2(rex_r, vex_reg, prefix));
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}
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}
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/*!
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* Set VEX prefix for REX as needed for two registers.
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*/
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void set_vex_modrm_and_rex(uint8_t reg,
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uint8_t rm,
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uint8_t mod,
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VEX3::LeadingBytes lb,
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bool rex_w = false) {
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bool rex_b = false;
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bool rex_r = false;
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if (rm >= 8) {
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rm -= 8;
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rex_b = true;
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}
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if (reg >= 8) {
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reg -= 8;
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rex_r = true;
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}
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ModRM modrm;
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modrm.mod = mod;
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modrm.reg_op = reg;
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modrm.rm = rm;
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set(modrm);
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if (rex_b || rex_w || lb != VEX3::LeadingBytes::P_0F) {
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// need three byte version
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set(VEX3(rex_w, rex_r, false, rex_b, lb));
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} else {
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// can get away with two byte version
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assert(lb == VEX3::LeadingBytes::P_0F); // vex2 implies 0x0f
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assert(!rex_b);
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assert(!rex_w);
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set(VEX2(rex_r));
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}
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}
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2020-08-29 22:41:46 -04:00
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void set_modrm_and_rex_for_reg_plus_reg_plus_s8(uint8_t reg,
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uint8_t addr1,
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uint8_t addr2,
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s8 offset,
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bool rex_w) {
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2020-08-29 21:04:21 -04:00
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bool rex_b = false, rex_r = false, rex_x = false;
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bool addr1_ext = false;
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bool addr2_ext = false;
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if (addr1 >= 8) {
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addr1 -= 8;
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addr1_ext = true;
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}
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if (addr2 >= 8) {
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addr2 -= 8;
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addr2_ext = true;
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}
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if (reg >= 8) {
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reg -= 8;
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rex_r = true;
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}
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ModRM modrm;
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2020-08-29 22:41:46 -04:00
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modrm.mod = 1; // no disp
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modrm.rm = 4; // sib!
|
2020-08-29 21:04:21 -04:00
|
|
|
modrm.reg_op = reg;
|
|
|
|
|
|
|
|
SIB sib;
|
|
|
|
sib.scale = 0;
|
|
|
|
|
|
|
|
Imm imm2(1, offset);
|
|
|
|
|
|
|
|
// default addr1 in index
|
2020-08-29 22:41:46 -04:00
|
|
|
if (addr1 == 4) {
|
2020-08-29 21:04:21 -04:00
|
|
|
sib.index = addr2;
|
|
|
|
sib.base = addr1;
|
|
|
|
rex_x = addr2_ext;
|
|
|
|
rex_b = addr1_ext;
|
|
|
|
} else {
|
|
|
|
// addr1 in index
|
|
|
|
sib.index = addr1;
|
|
|
|
sib.base = addr2;
|
|
|
|
rex_x = addr1_ext;
|
|
|
|
rex_b = addr2_ext;
|
|
|
|
}
|
|
|
|
assert(sib.index != 4);
|
|
|
|
|
2020-08-29 22:41:46 -04:00
|
|
|
if (rex_b || rex_w || rex_r || rex_x) {
|
2020-08-29 21:04:21 -04:00
|
|
|
set(REX(rex_w, rex_r, rex_x, rex_b));
|
|
|
|
}
|
|
|
|
|
|
|
|
set(modrm);
|
|
|
|
set(sib);
|
|
|
|
set_disp(imm2);
|
|
|
|
}
|
|
|
|
|
2020-12-30 15:33:51 -05:00
|
|
|
void set_vex_modrm_and_rex_for_reg_plus_reg_plus_s8(uint8_t reg,
|
|
|
|
uint8_t addr1,
|
|
|
|
uint8_t addr2,
|
|
|
|
s8 offset,
|
|
|
|
VEX3::LeadingBytes lb,
|
|
|
|
bool rex_w) {
|
|
|
|
bool rex_b = false, rex_r = false, rex_x = false;
|
|
|
|
bool addr1_ext = false;
|
|
|
|
bool addr2_ext = false;
|
|
|
|
|
|
|
|
if (addr1 >= 8) {
|
|
|
|
addr1 -= 8;
|
|
|
|
addr1_ext = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (addr2 >= 8) {
|
|
|
|
addr2 -= 8;
|
|
|
|
addr2_ext = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (reg >= 8) {
|
|
|
|
reg -= 8;
|
|
|
|
rex_r = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
ModRM modrm;
|
|
|
|
modrm.mod = 1; // no disp
|
|
|
|
modrm.rm = 4; // sib!
|
|
|
|
modrm.reg_op = reg;
|
|
|
|
|
|
|
|
SIB sib;
|
|
|
|
sib.scale = 0;
|
|
|
|
|
|
|
|
Imm imm2(1, offset);
|
|
|
|
|
|
|
|
// default addr1 in index
|
|
|
|
if (addr1 == 4) {
|
|
|
|
sib.index = addr2;
|
|
|
|
sib.base = addr1;
|
|
|
|
rex_x = addr2_ext;
|
|
|
|
rex_b = addr1_ext;
|
|
|
|
} else {
|
|
|
|
// addr1 in index
|
|
|
|
sib.index = addr1;
|
|
|
|
sib.base = addr2;
|
|
|
|
rex_x = addr1_ext;
|
|
|
|
rex_b = addr2_ext;
|
|
|
|
}
|
|
|
|
assert(sib.index != 4);
|
|
|
|
|
|
|
|
if (rex_b || rex_w || rex_x || lb != VEX3::LeadingBytes::P_0F) {
|
|
|
|
// need three byte version
|
|
|
|
set(VEX3(rex_w, rex_r, rex_x, rex_b, lb));
|
|
|
|
} else {
|
|
|
|
assert(lb == VEX3::LeadingBytes::P_0F); // vex2 implies 0x0f
|
|
|
|
assert(!rex_b);
|
|
|
|
assert(!rex_w);
|
|
|
|
assert(!rex_x);
|
|
|
|
set(VEX2(rex_r));
|
|
|
|
}
|
|
|
|
|
|
|
|
set(modrm);
|
|
|
|
set(sib);
|
|
|
|
set_disp(imm2);
|
|
|
|
}
|
|
|
|
|
2020-08-29 22:41:46 -04:00
|
|
|
void set_modrm_and_rex_for_reg_plus_reg_plus_s32(uint8_t reg,
|
|
|
|
uint8_t addr1,
|
|
|
|
uint8_t addr2,
|
2020-08-30 10:56:42 -04:00
|
|
|
s32 offset,
|
2020-08-29 22:41:46 -04:00
|
|
|
bool rex_w) {
|
2020-08-29 21:04:21 -04:00
|
|
|
bool rex_b = false, rex_r = false, rex_x = false;
|
|
|
|
bool addr1_ext = false;
|
|
|
|
bool addr2_ext = false;
|
|
|
|
|
|
|
|
if (addr1 >= 8) {
|
|
|
|
addr1 -= 8;
|
|
|
|
addr1_ext = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (addr2 >= 8) {
|
|
|
|
addr2 -= 8;
|
|
|
|
addr2_ext = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (reg >= 8) {
|
|
|
|
reg -= 8;
|
|
|
|
rex_r = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
ModRM modrm;
|
2020-08-29 22:41:46 -04:00
|
|
|
modrm.mod = 2; // no disp
|
|
|
|
modrm.rm = 4; // sib!
|
2020-08-29 21:04:21 -04:00
|
|
|
modrm.reg_op = reg;
|
|
|
|
|
|
|
|
SIB sib;
|
|
|
|
sib.scale = 0;
|
|
|
|
|
|
|
|
Imm imm2(4, offset);
|
|
|
|
|
|
|
|
// default addr1 in index
|
2020-08-29 22:41:46 -04:00
|
|
|
if (addr1 == 4) {
|
2020-08-29 21:04:21 -04:00
|
|
|
sib.index = addr2;
|
|
|
|
sib.base = addr1;
|
|
|
|
rex_x = addr2_ext;
|
|
|
|
rex_b = addr1_ext;
|
|
|
|
} else {
|
|
|
|
// addr1 in index
|
|
|
|
sib.index = addr1;
|
|
|
|
sib.base = addr2;
|
|
|
|
rex_x = addr1_ext;
|
|
|
|
rex_b = addr2_ext;
|
|
|
|
}
|
|
|
|
assert(sib.index != 4);
|
|
|
|
|
2020-08-29 22:41:46 -04:00
|
|
|
if (rex_b || rex_w || rex_r || rex_x) {
|
2020-08-29 21:04:21 -04:00
|
|
|
set(REX(rex_w, rex_r, rex_x, rex_b));
|
|
|
|
}
|
|
|
|
|
|
|
|
set(modrm);
|
|
|
|
set(sib);
|
|
|
|
set_disp(imm2);
|
|
|
|
}
|
|
|
|
|
2020-12-30 15:33:51 -05:00
|
|
|
void set_vex_modrm_and_rex_for_reg_plus_reg_plus_s32(uint8_t reg,
|
|
|
|
uint8_t addr1,
|
|
|
|
uint8_t addr2,
|
|
|
|
s32 offset,
|
|
|
|
VEX3::LeadingBytes lb,
|
|
|
|
bool rex_w) {
|
|
|
|
bool rex_b = false, rex_r = false, rex_x = false;
|
|
|
|
bool addr1_ext = false;
|
|
|
|
bool addr2_ext = false;
|
|
|
|
|
|
|
|
if (addr1 >= 8) {
|
|
|
|
addr1 -= 8;
|
|
|
|
addr1_ext = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (addr2 >= 8) {
|
|
|
|
addr2 -= 8;
|
|
|
|
addr2_ext = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (reg >= 8) {
|
|
|
|
reg -= 8;
|
|
|
|
rex_r = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
ModRM modrm;
|
|
|
|
modrm.mod = 2; // no disp
|
|
|
|
modrm.rm = 4; // sib!
|
|
|
|
modrm.reg_op = reg;
|
|
|
|
|
|
|
|
SIB sib;
|
|
|
|
sib.scale = 0;
|
|
|
|
|
|
|
|
Imm imm2(4, offset);
|
|
|
|
|
|
|
|
// default addr1 in index
|
|
|
|
if (addr1 == 4) {
|
|
|
|
sib.index = addr2;
|
|
|
|
sib.base = addr1;
|
|
|
|
rex_x = addr2_ext;
|
|
|
|
rex_b = addr1_ext;
|
|
|
|
} else {
|
|
|
|
// addr1 in index
|
|
|
|
sib.index = addr1;
|
|
|
|
sib.base = addr2;
|
|
|
|
rex_x = addr1_ext;
|
|
|
|
rex_b = addr2_ext;
|
|
|
|
}
|
|
|
|
assert(sib.index != 4);
|
|
|
|
|
|
|
|
if (rex_b || rex_w || rex_x || lb != VEX3::LeadingBytes::P_0F) {
|
|
|
|
// need three byte version
|
|
|
|
set(VEX3(rex_w, rex_r, rex_x, rex_b, lb));
|
|
|
|
} else {
|
|
|
|
assert(lb == VEX3::LeadingBytes::P_0F); // vex2 implies 0x0f
|
|
|
|
assert(!rex_b);
|
|
|
|
assert(!rex_w);
|
|
|
|
assert(!rex_x);
|
|
|
|
set(VEX2(rex_r));
|
|
|
|
}
|
|
|
|
|
|
|
|
set(modrm);
|
|
|
|
set(sib);
|
|
|
|
set_disp(imm2);
|
|
|
|
}
|
|
|
|
|
2020-08-29 22:41:46 -04:00
|
|
|
void set_modrm_and_rex_for_reg_plus_reg_addr(uint8_t reg,
|
|
|
|
uint8_t addr1,
|
|
|
|
uint8_t addr2,
|
|
|
|
bool rex_w = false,
|
|
|
|
bool rex_always = false) {
|
2020-08-29 19:13:29 -04:00
|
|
|
bool rex_b = false, rex_r = false, rex_x = false;
|
|
|
|
bool addr1_ext = false;
|
|
|
|
bool addr2_ext = false;
|
|
|
|
|
|
|
|
if (addr1 >= 8) {
|
|
|
|
addr1 -= 8;
|
|
|
|
addr1_ext = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (addr2 >= 8) {
|
|
|
|
addr2 -= 8;
|
|
|
|
addr2_ext = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (reg >= 8) {
|
|
|
|
reg -= 8;
|
|
|
|
rex_r = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
ModRM modrm;
|
2020-08-29 22:41:46 -04:00
|
|
|
modrm.mod = 0; // no disp
|
|
|
|
modrm.rm = 4; // sib!
|
2020-08-29 19:13:29 -04:00
|
|
|
modrm.reg_op = reg;
|
|
|
|
|
|
|
|
SIB sib;
|
|
|
|
sib.scale = 0;
|
|
|
|
|
2020-08-29 22:41:46 -04:00
|
|
|
if (addr1 == 5 && addr2 == 5) {
|
2020-08-29 19:13:29 -04:00
|
|
|
sib.index = addr1;
|
|
|
|
sib.base = addr2;
|
|
|
|
rex_x = addr1_ext;
|
|
|
|
rex_b = addr2_ext;
|
|
|
|
modrm.mod = 1;
|
2020-08-29 21:04:21 -04:00
|
|
|
set_disp(Imm(1, 0));
|
2020-08-29 19:13:29 -04:00
|
|
|
|
|
|
|
} else {
|
|
|
|
// default addr1 in index
|
|
|
|
bool flipped = (addr1 == 4) || (addr2 == 5);
|
|
|
|
|
2020-08-29 22:41:46 -04:00
|
|
|
if (flipped) {
|
2020-08-29 19:13:29 -04:00
|
|
|
sib.index = addr2;
|
|
|
|
sib.base = addr1;
|
|
|
|
rex_x = addr2_ext;
|
|
|
|
rex_b = addr1_ext;
|
|
|
|
} else {
|
|
|
|
// addr1 in index
|
|
|
|
sib.index = addr1;
|
|
|
|
sib.base = addr2;
|
|
|
|
rex_x = addr1_ext;
|
|
|
|
rex_b = addr2_ext;
|
|
|
|
}
|
|
|
|
assert(sib.base != 5);
|
|
|
|
assert(sib.index != 4);
|
|
|
|
}
|
|
|
|
|
2020-08-29 22:41:46 -04:00
|
|
|
if (rex_b || rex_w || rex_r || rex_x || rex_always) {
|
2020-08-29 19:13:29 -04:00
|
|
|
set(REX(rex_w, rex_r, rex_x, rex_b));
|
|
|
|
}
|
|
|
|
|
|
|
|
set(modrm);
|
|
|
|
set(sib);
|
|
|
|
}
|
|
|
|
|
2020-12-30 15:33:51 -05:00
|
|
|
void set_vex_modrm_and_rex_for_reg_plus_reg_addr(uint8_t reg,
|
|
|
|
uint8_t addr1,
|
|
|
|
uint8_t addr2,
|
|
|
|
VEX3::LeadingBytes lb,
|
|
|
|
bool rex_w = false) {
|
|
|
|
bool rex_b = false, rex_r = false, rex_x = false;
|
|
|
|
bool addr1_ext = false;
|
|
|
|
bool addr2_ext = false;
|
|
|
|
|
|
|
|
if (addr1 >= 8) {
|
|
|
|
addr1 -= 8;
|
|
|
|
addr1_ext = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (addr2 >= 8) {
|
|
|
|
addr2 -= 8;
|
|
|
|
addr2_ext = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (reg >= 8) {
|
|
|
|
reg -= 8;
|
|
|
|
rex_r = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
ModRM modrm;
|
|
|
|
modrm.mod = 0; // no disp
|
|
|
|
modrm.rm = 4; // sib!
|
|
|
|
modrm.reg_op = reg;
|
|
|
|
|
|
|
|
SIB sib;
|
|
|
|
sib.scale = 0;
|
|
|
|
|
|
|
|
if (addr1 == 5 && addr2 == 5) {
|
|
|
|
sib.index = addr1;
|
|
|
|
sib.base = addr2;
|
|
|
|
rex_x = addr1_ext;
|
|
|
|
rex_b = addr2_ext;
|
|
|
|
modrm.mod = 1;
|
|
|
|
set_disp(Imm(1, 0));
|
|
|
|
|
|
|
|
} else {
|
|
|
|
// default addr1 in index
|
|
|
|
bool flipped = (addr1 == 4) || (addr2 == 5);
|
|
|
|
|
|
|
|
if (flipped) {
|
|
|
|
sib.index = addr2;
|
|
|
|
sib.base = addr1;
|
|
|
|
rex_x = addr2_ext;
|
|
|
|
rex_b = addr1_ext;
|
|
|
|
} else {
|
|
|
|
// addr1 in index
|
|
|
|
sib.index = addr1;
|
|
|
|
sib.base = addr2;
|
|
|
|
rex_x = addr1_ext;
|
|
|
|
rex_b = addr2_ext;
|
|
|
|
}
|
|
|
|
assert(sib.base != 5);
|
|
|
|
assert(sib.index != 4);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (rex_b || rex_w || rex_x || lb != VEX3::LeadingBytes::P_0F) {
|
|
|
|
// need three byte version
|
|
|
|
set(VEX3(rex_w, rex_r, rex_x, rex_b, lb));
|
|
|
|
} else {
|
|
|
|
assert(lb == VEX3::LeadingBytes::P_0F); // vex2 implies 0x0f
|
|
|
|
assert(!rex_b);
|
|
|
|
assert(!rex_w);
|
|
|
|
assert(!rex_x);
|
|
|
|
set(VEX2(rex_r));
|
|
|
|
}
|
|
|
|
|
|
|
|
set(modrm);
|
|
|
|
set(sib);
|
|
|
|
}
|
|
|
|
|
2020-08-22 22:30:12 -04:00
|
|
|
/*!
|
|
|
|
* Set modrm and rex as needed for two regs for an addressing mode.
|
|
|
|
* Will set SIB if R12 or RSP indexing is used.
|
|
|
|
*/
|
2020-08-29 19:13:29 -04:00
|
|
|
void set_modrm_and_rex_for_reg_addr(uint8_t reg, uint8_t rm, bool rex_w = false) {
|
2020-08-22 22:30:12 -04:00
|
|
|
bool rex_b = false, rex_r = false;
|
|
|
|
|
2020-08-26 01:21:33 -04:00
|
|
|
if (rm >= 8) {
|
2020-08-22 22:30:12 -04:00
|
|
|
rm -= 8;
|
|
|
|
rex_b = true;
|
|
|
|
}
|
|
|
|
|
2020-08-26 01:21:33 -04:00
|
|
|
if (reg >= 8) {
|
2020-08-22 22:30:12 -04:00
|
|
|
reg -= 8;
|
|
|
|
rex_r = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
ModRM modrm;
|
2020-08-29 19:13:29 -04:00
|
|
|
modrm.mod = 0;
|
2020-08-22 22:30:12 -04:00
|
|
|
modrm.reg_op = reg;
|
|
|
|
modrm.rm = rm;
|
|
|
|
|
2020-08-26 01:21:33 -04:00
|
|
|
if (rm == 4) {
|
2020-08-22 22:30:12 -04:00
|
|
|
SIB sib;
|
|
|
|
sib.scale = 0;
|
|
|
|
sib.base = 4;
|
|
|
|
sib.index = 4;
|
|
|
|
|
|
|
|
set(sib);
|
|
|
|
}
|
|
|
|
|
2020-08-29 19:13:29 -04:00
|
|
|
if (rm == 5) {
|
|
|
|
modrm.mod = 1; // 1 byte imm
|
2020-08-29 21:04:21 -04:00
|
|
|
set_disp(Imm(1, 0));
|
2020-08-29 19:13:29 -04:00
|
|
|
}
|
|
|
|
|
|
|
|
set(modrm);
|
2020-08-26 01:21:33 -04:00
|
|
|
if (rex_b || rex_w || rex_r) {
|
2020-08-22 22:30:12 -04:00
|
|
|
set(REX(rex_w, rex_r, false, rex_b));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-08-30 20:39:39 -04:00
|
|
|
void set_modrm_and_rex_for_rip_plus_s32(uint8_t reg, s32 offset, bool rex_w = false) {
|
|
|
|
bool rex_r = false;
|
|
|
|
|
|
|
|
if (reg >= 8) {
|
|
|
|
reg -= 8;
|
|
|
|
rex_r = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
ModRM modrm;
|
|
|
|
modrm.mod = 0;
|
|
|
|
modrm.reg_op = reg;
|
|
|
|
modrm.rm = 5; // use the RIP addressing mode
|
|
|
|
set(modrm);
|
|
|
|
|
|
|
|
if (rex_r || rex_w) {
|
|
|
|
set(REX(rex_w, rex_r, false, false));
|
|
|
|
}
|
|
|
|
|
|
|
|
set_disp(Imm(4, offset));
|
|
|
|
}
|
|
|
|
|
2020-08-22 22:30:12 -04:00
|
|
|
void add_rex() {
|
2020-08-26 01:21:33 -04:00
|
|
|
if (!set_rex) {
|
2020-08-22 22:30:12 -04:00
|
|
|
set(REX());
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-12-30 15:33:51 -05:00
|
|
|
void set_vex_modrm_and_rex_for_rip_plus_s32(uint8_t reg,
|
|
|
|
s32 offset,
|
|
|
|
VEX3::LeadingBytes lb = VEX3::LeadingBytes::P_0F,
|
|
|
|
bool rex_w = false) {
|
|
|
|
bool rex_r = false;
|
|
|
|
|
|
|
|
if (reg >= 8) {
|
|
|
|
reg -= 8;
|
|
|
|
rex_r = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
ModRM modrm;
|
|
|
|
modrm.mod = 0;
|
|
|
|
modrm.reg_op = reg;
|
|
|
|
modrm.rm = 5; // use the RIP addressing mode
|
|
|
|
set(modrm);
|
|
|
|
|
|
|
|
if (rex_w || lb != VEX3::LeadingBytes::P_0F) {
|
|
|
|
// need three byte version
|
|
|
|
set(VEX3(rex_w, rex_r, false, false, lb));
|
|
|
|
} else {
|
|
|
|
assert(lb == VEX3::LeadingBytes::P_0F); // vex2 implies 0x0f
|
|
|
|
assert(!rex_w);
|
|
|
|
set(VEX2(rex_r));
|
|
|
|
}
|
|
|
|
|
|
|
|
set_disp(Imm(4, offset));
|
|
|
|
}
|
|
|
|
|
2020-08-22 22:30:12 -04:00
|
|
|
/*!
|
|
|
|
* Set up modrm and rex for the commonly used 32-bit immediate displacement indexing mode.
|
|
|
|
*/
|
|
|
|
void set_modrm_rex_sib_for_reg_reg_disp32(uint8_t reg, uint8_t mod, uint8_t rm, bool rex_w) {
|
|
|
|
ModRM modrm;
|
|
|
|
|
|
|
|
bool rex_r = false;
|
2020-08-26 01:21:33 -04:00
|
|
|
if (reg >= 8) {
|
2020-08-22 22:30:12 -04:00
|
|
|
reg -= 8;
|
|
|
|
rex_r = true;
|
|
|
|
}
|
|
|
|
modrm.reg_op = reg;
|
|
|
|
|
|
|
|
modrm.mod = mod;
|
|
|
|
|
2020-08-26 01:21:33 -04:00
|
|
|
modrm.rm = 4; // use sib
|
2020-08-22 22:30:12 -04:00
|
|
|
|
|
|
|
SIB sib;
|
|
|
|
sib.scale = 0;
|
|
|
|
sib.index = 4;
|
|
|
|
bool rex_b = false;
|
2020-08-26 01:21:33 -04:00
|
|
|
if (rm >= 8) {
|
2020-08-22 22:30:12 -04:00
|
|
|
rex_b = true;
|
|
|
|
rm -= 8;
|
|
|
|
}
|
|
|
|
|
|
|
|
sib.base = rm;
|
|
|
|
|
|
|
|
set(modrm);
|
|
|
|
set(sib);
|
|
|
|
|
2020-08-26 01:21:33 -04:00
|
|
|
if (rex_r || rex_w || rex_b) {
|
2020-08-22 22:30:12 -04:00
|
|
|
set(REX(rex_w, rex_r, false, rex_b));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/*!
|
|
|
|
* Get the position of the disp immediate relative to the start of the instruction
|
|
|
|
*/
|
|
|
|
int offset_of_disp() const {
|
2020-08-26 01:21:33 -04:00
|
|
|
if (is_null)
|
|
|
|
return 0;
|
2020-08-22 22:30:12 -04:00
|
|
|
assert(set_disp_imm);
|
|
|
|
int offset = 0;
|
2020-12-30 15:33:51 -05:00
|
|
|
offset += n_vex;
|
2020-08-26 01:21:33 -04:00
|
|
|
if (set_rex)
|
|
|
|
offset++;
|
|
|
|
offset++; // opcode
|
|
|
|
if (op2_set)
|
|
|
|
offset++;
|
|
|
|
if (op3_set)
|
|
|
|
offset++;
|
|
|
|
if (set_modrm)
|
|
|
|
offset++;
|
|
|
|
if (set_sib)
|
|
|
|
offset++;
|
2020-08-22 22:30:12 -04:00
|
|
|
return offset;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*!
|
|
|
|
* Get the position of the imm immediate relative to the start of the instruction
|
|
|
|
*/
|
|
|
|
int offset_of_imm() const {
|
2020-08-26 01:21:33 -04:00
|
|
|
if (is_null)
|
|
|
|
return 0;
|
2020-08-22 22:30:12 -04:00
|
|
|
assert(set_imm);
|
|
|
|
int offset = 0;
|
2020-12-30 15:33:51 -05:00
|
|
|
offset += n_vex;
|
2020-08-26 01:21:33 -04:00
|
|
|
if (set_rex)
|
|
|
|
offset++;
|
|
|
|
offset++; // opcode
|
|
|
|
if (op2_set)
|
|
|
|
offset++;
|
|
|
|
if (op3_set)
|
|
|
|
offset++;
|
|
|
|
if (set_modrm)
|
|
|
|
offset++;
|
|
|
|
if (set_sib)
|
|
|
|
offset++;
|
|
|
|
if (set_disp_imm)
|
|
|
|
offset += disp.size;
|
2020-08-22 22:30:12 -04:00
|
|
|
return offset;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*!
|
|
|
|
* Emit into a buffer and return how many bytes written (can be zero)
|
|
|
|
*/
|
|
|
|
uint8_t emit(uint8_t* buffer) const {
|
2020-08-26 01:21:33 -04:00
|
|
|
if (is_null)
|
|
|
|
return 0;
|
2020-08-22 22:30:12 -04:00
|
|
|
uint8_t count = 0;
|
2020-12-30 15:33:51 -05:00
|
|
|
|
|
|
|
for (int i = 0; i < n_vex; i++) {
|
|
|
|
buffer[count++] = vex[i];
|
|
|
|
}
|
|
|
|
|
2020-08-26 01:21:33 -04:00
|
|
|
if (set_rex) {
|
2020-08-22 22:30:12 -04:00
|
|
|
buffer[count++] = m_rex;
|
|
|
|
}
|
|
|
|
|
|
|
|
buffer[count++] = op;
|
|
|
|
|
2020-08-26 01:21:33 -04:00
|
|
|
if (op2_set) {
|
2020-08-22 22:30:12 -04:00
|
|
|
buffer[count++] = op2;
|
|
|
|
}
|
|
|
|
|
2020-08-26 01:21:33 -04:00
|
|
|
if (op3_set) {
|
2020-08-22 22:30:12 -04:00
|
|
|
buffer[count++] = op3;
|
|
|
|
}
|
|
|
|
|
2020-08-26 01:21:33 -04:00
|
|
|
if (set_modrm) {
|
2020-08-22 22:30:12 -04:00
|
|
|
buffer[count++] = m_modrm;
|
|
|
|
}
|
|
|
|
|
2020-08-26 01:21:33 -04:00
|
|
|
if (set_sib) {
|
2020-08-22 22:30:12 -04:00
|
|
|
buffer[count++] = m_sib;
|
|
|
|
}
|
|
|
|
|
2020-08-26 01:21:33 -04:00
|
|
|
if (set_disp_imm) {
|
|
|
|
for (int i = 0; i < disp.size; i++) {
|
2020-08-22 22:30:12 -04:00
|
|
|
buffer[count++] = disp.v_arr[i];
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-08-26 01:21:33 -04:00
|
|
|
if (set_imm) {
|
|
|
|
for (int i = 0; i < imm.size; i++) {
|
2020-08-22 22:30:12 -04:00
|
|
|
buffer[count++] = imm.v_arr[i];
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return count;
|
|
|
|
}
|
2020-09-02 16:24:13 -04:00
|
|
|
|
|
|
|
uint8_t length() const {
|
|
|
|
if (is_null)
|
|
|
|
return 0;
|
|
|
|
uint8_t count = 0;
|
2020-12-30 15:33:51 -05:00
|
|
|
|
|
|
|
count += n_vex;
|
|
|
|
|
2020-09-02 16:24:13 -04:00
|
|
|
if (set_rex) {
|
|
|
|
count++;
|
|
|
|
}
|
|
|
|
|
|
|
|
count++;
|
|
|
|
|
|
|
|
if (op2_set) {
|
|
|
|
count++;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (op3_set) {
|
|
|
|
count++;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (set_modrm) {
|
|
|
|
count++;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (set_sib) {
|
|
|
|
count++;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (set_disp_imm) {
|
|
|
|
for (int i = 0; i < disp.size; i++) {
|
|
|
|
count++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (set_imm) {
|
|
|
|
for (int i = 0; i < imm.size; i++) {
|
|
|
|
count++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return count;
|
|
|
|
}
|
2020-08-22 22:30:12 -04:00
|
|
|
};
|
2020-08-29 19:13:29 -04:00
|
|
|
} // namespace emitter
|
2020-08-22 22:30:12 -04:00
|
|
|
|
2020-08-29 19:13:29 -04:00
|
|
|
#endif // JAK_INSTRUCTION_H
|