mirror of
https://github.com/open-goal/jak-project.git
synced 2024-10-20 00:57:44 -04:00
748 lines
20 KiB
Plaintext
748 lines
20 KiB
Plaintext
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// The actual "tfrag" type. This only lives on the EE and gets converted to DMA data.
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// some of the DMA data is pointers to chains that live in the static level data.
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// other is colors that are looked up from the palette (on the EE!) then thrown in the
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// double-buffered frame global buffer.
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(deftype tfragment (drawable)
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(
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(color-index uint16 :offset 6)
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(debug-data tfragment-debug-data :offset 8)
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(color-indices uint32 :offset 12)
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(colors uint32 :offset 12)
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(dma-chain uint32 3 :offset-assert 32)
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(dma-common uint32 :offset 32)
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(dma-level-0 uint32 :offset 32)
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(dma-base uint32 :offset 36)
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(dma-level-1 uint32 :offset 40)
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(dma-qwc uint8 4 :offset 44)
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(shader (inline-array adgif-shader) :offset 48)
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(num-shaders uint8 :offset 52)
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(num-base-colors uint8 :offset 53)
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(num-level0-colors uint8 :offset 54)
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(num-level1-colors uint8 :offset 55)
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(color-offset uint8 :offset 56)
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(color-count uint8 :offset 57)
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(pad0 uint8 :offset 58)
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(pad1 uint8 :offset 59)
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(generic generic-tfragment :offset-assert 60)
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(generic-u32 uint32 :offset 60) ;; added
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)
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:method-count-assert 18
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:size-assert #x40
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:flag-assert #x1200000040
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)
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// This is the temp/debug structure used for the EE code
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(deftype tfrag-work (structure)
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((base-tmpl dma-packet :inline :offset-assert 0)
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(level-0-tmpl dma-packet :inline :offset-assert 16)
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(common-tmpl dma-packet :inline :offset-assert 32)
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(level-1-tmpl dma-packet :inline :offset-assert 48)
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(color-tmpl dma-packet :inline :offset-assert 64)
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(frag-dists vector :inline :offset-assert 80)
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(max-dist vector :inline :offset-assert 96)
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(min-dist vector :inline :offset-assert 112)
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(color-ptr vector4w :inline :offset-assert 128)
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(tr-stat-tfrag tr-stat :offset-assert 144)
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(tr-stat-tfrag-near tr-stat :offset-assert 148)
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(vu1-enable-tfrag int32 :offset-assert 152)
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(vu1-enable-tfrag-near int32 :offset-assert 156)
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(cur-vis-bits uint32 :offset-assert 160)
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(end-vis-bits uint32 :offset-assert 164)
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(src-ptr uint32 :offset-assert 168)
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(last-call uint32 :offset-assert 172)
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(dma-buffer basic :offset-assert 176)
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(test-id uint32 :offset-assert 180)
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(wait-from-spr uint32 :offset-assert 184)
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(wait-to-spr uint32 :offset-assert 188)
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(near-wait-from-spr uint32 :offset-assert 192)
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(near-wait-to-spr uint32 :offset-assert 196)
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)
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:method-count-assert 9
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:size-assert #xc8
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:flag-assert #x9000000c8
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)
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*/
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// base vifs:
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// ??
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// t3
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// l0:
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// ??
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// t3
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// common:
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// ??
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// t3
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// color
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// ??
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// 12 sb color-offset
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// 14 sb num colors, 4 aligned.
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/*
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; .function draw-inline-array-tfrag
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; there's two double-buffered spad buffers + culling data
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;; arguments:
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;; a0 - occlusion cull list (on spad)
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;; a1 - tfrags
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;; a2 - num tfrags
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;; a3 - dma buf
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;; constants:
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;; t0 = *tfrag-work*
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;; t1 = SPR FROM
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;; t2 = 0x14000000 ??
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;; t4 = SPR TO
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;; vars:
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;; v1 = ptr to dma buffer data
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;; t5 = SPR BUFFER 0 (tfrags)
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;; a3 = SPR BUFFER 1
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;; t3 = ?? (init to 0)
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;; t6 = spr buffer 1 use (qwc)
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;; vf3 = frag-dists
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;; vf1 = (1, 1, 1, 1)
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;; vf2 = bsphere
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B0:
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L40:
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TFRAG INITIALIZE
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;; set up constants
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daddiu sp, sp, -128
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sd ra, 0(sp)
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sq s0, 16(sp)
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sq s1, 32(sp)
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sq s2, 48(sp)
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sq s3, 64(sp)
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sq s4, 80(sp)
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sq s5, 96(sp)
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sq gp, 112(sp)
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lui t2, 5120 = (0x14000000), a constant (mscal)
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lw v1, 4(a3) (-> dma-buf base)
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lui t3, 4096 = (0x10000000)
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lui t1, 4096 = (0x10000000)
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sync.l
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cache dxwbin v1, 0
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sync.l
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cache dxwbin v1, 1
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sync.l
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lw t0, *tfrag-work*(s7)
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ori t4, t3, 54272 = (0x1000D400) SPR TO
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ori t1, t1, 53248 = (0x1000D000) SPR FROM
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lui t5, 28672 = (0x70000000)
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lqc2 vf3, 80(t0) = (-> *tfrag-work* frag-dists)
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sw a3, 176(t0) (set! (-> *tfrag-work* dma-buffer) dma-ptr)
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ori a3, t5, 2064 setup buffer 1
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addiu t3, r0, 0 t3 = 0
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ori t5, t5, 1040 setup buffer 0
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vmaxw.xyzw vf1, vf0, vf0 vf1 = (1, 1, 1, 1)
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lh t7, 0(a0) vis cull load
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lqc2 vf4, 96(t0) max-dist
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addiu a1, a1, -4 remove basic offset
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addiu t6, r0, 0 t6 = 0
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or ra, a3, r0 ra = SPAD BUFFER 1
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SKIP TO FIRST VISIBLE
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;; skips ahead until we find some visible tfrags.
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B1:
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L41:
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bne t7, r0, L42
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sll r0, r0, 0
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B2:
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addiu a0, a0, 2 ;; + 16 bits in the vis list
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addiu a1, a1, 1024 ;; 16 * 0x40 = 1024 bytes in tfrag list
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daddiu a2, a2, -16 ;; num tfrags -= 16
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lh t7, 0(a0) ;; next vis
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blez a2, L69_CLEANUP ;; no visible tfrags, abort!
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sll r0, r0, 0
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B3:
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beq r0, r0, L41 ;; keep looking
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sll r0, r0, 0
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WAIT_FOR_PREV_DMA
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;; waits for any previously running spad dma transfer to end
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B4:
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L42:
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lw t7, 0(t4)
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sll r0, r0, 0
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sll r0, r0, 0
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sll r0, r0, 0
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andi t7, t7, 256
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sll r0, r0, 0
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bne t7, r0, L42
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sll r0, r0, 0
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INIT_FIRST_SPAD_TO
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;; initializes the first scratchpad upload of tfrags
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B5:
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sw a1, 16(t4) ;; madr = a1
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xori t7, t5, 1024 ;; t7 = upload addr of tfrags double buffer
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sw t7, 128(t4) ;; sadr
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addiu t7, r0, 64 ;; 64 qw = 16 tfrags
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sw t7, 32(t4) ;; qwc
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addiu t7, r0, 256 ;; go
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sw t7, 0(t4) ;; go!
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sll r0, r0, 0
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TFRAG MAIN LOOP TOP
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B6:
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L43:
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or gp, a0, r0 ;; gp = temp addr of vis list
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xori t5, t5, 1024 ;; toggle to addr of upload tfrags
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daddiu a0, a0, 2 ;; advance vis list ptr (16 tfrags)
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or t9, a0, r0 ;; t9 = temp addr of next vis list
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or t8, t5, r0 ;; t8 = tfrags to use
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;; next, let's find next block of visible tfrags so we can start it's dma early
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daddiu t7, a2, -16 ;; t7 = tfrags left after this loop
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bgtz t7, L45 ;; if we have them left, jump
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lh t7, 0(a0) ;; and load their vis
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B7:
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beq r0, r0, L48 ;; none left, skip dma kickoff.
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sll r0, r0, 0
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B8:
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L44:
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daddiu a2, a2, -16 ;; skip invisible block (dec tfrag counter)
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addiu a0, a0, 2 ;; increment vis list
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blez a2, L48 ;; did we get to the end of the tfrag list?
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lh t7, 0(a0) ;; check vis again.
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B9:
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sll r0, r0, 0
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sll r0, r0, 0
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B10:
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L45:
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beq t7, r0, L44 ;; we have tfrags left. if 0, they are all hidden, so loop
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addiu a1, a1, 1024 ;; and advance upload pointer (not done at all yet)
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;; we reach here if we have tfrags left after this block.
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;; so let's upload the next ones to the scratchpad so they are ready by next time.
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B11:
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L46:
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lw t7, 0(t4) ;; make sure to-spr is done
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sll r0, r0, 0
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sll r0, r0, 0
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sll r0, r0, 0
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andi t7, t7, 256
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sll r0, r0, 0
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beq t7, r0, L47
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sll r0, r0, 0
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B12:
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sll r0, r0, 0
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lw t7, 188(t0)
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sll r0, r0, 0
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sll r0, r0, 0
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sll r0, r0, 0
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daddiu t7, t7, 1 ;; counting how many times we wait
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sll r0, r0, 0
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sw t7, 188(t0)
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beq r0, r0, L46
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sll r0, r0, 0
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B13:
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L47:
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sw a1, 16(t4) ;; start the to!
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xori t7, t5, 1024
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sw t7, 128(t4)
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addiu t7, r0, 64
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sw t7, 32(t4)
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addiu t7, r0, 256
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beq r0, r0, L49 ;; skip ahead
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sw t7, 0(t4)
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;; only reach here if we dont have any more spr to's
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;; still need to sync the to for the block we're about to process
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B14:
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L48:
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lw t7, 0(t4)
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sll r0, r0, 0
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sll r0, r0, 0
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sll r0, r0, 0
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andi t7, t7, 256
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sll r0, r0, 0
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beq t7, r0, L49
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sll r0, r0, 0
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B15:
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sll r0, r0, 0
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lw t7, 188(t0)
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sll r0, r0, 0
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sll r0, r0, 0
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sll r0, r0, 0
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daddiu t7, t7, 1
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sll r0, r0, 0
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sw t7, 188(t0)
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beq r0, r0, L48
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sll r0, r0, 0
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;; common op start
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;; at this point:
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;; t8 is our spad tfrag buffer, with 16 tfrags. at least 1 is visible.
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;; gp is our vis-list pointer
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;; we run through this loop 2x, each time doing 8 tfrags.
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B16:
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L49:
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lb t7, 0(gp) ;; load first 8 frag vis bits
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addiu gp, gp, 1 ;; inc vis bit ptr.
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sll r0, r0, 0
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sw gp, 160(t0) ;; store cur-vis-bits
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bne t7, r0, L50 ;; are any visible in the first 8?
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sw t9, 164(t0) ;; set end-vis-bits (why?)
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B17: ;; none are visible
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daddiu a2, a2, -8 ;; dec tfrags
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addiu t8, t8, 512 ;; skip tfrags
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beq r0, r0, L65 ;; skip ahead!
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sll r0, r0, 0
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B18:
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L50:
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addiu t9, r0, 128 ;; vis mask init (gets shifted in each run of the 8-loop)
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lqc2 vf2, 16(t8) ;; bsphere load
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B19:
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L51:
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daddiu gp, t6, -124 ;; are we full of stuff in buffer 1?
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sll r0, r0, 0
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blez gp, L54
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sll r0, r0, 0
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B20:
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L52:
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lw ra, 0(t1) ;; wait for spr-from
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sll r0, r0, 0
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sll r0, r0, 0
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sll r0, r0, 0
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andi ra, ra, 256
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sll r0, r0, 0
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beq ra, r0, L53
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sll r0, r0, 0
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B21:
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sll r0, r0, 0 ;; count it
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lw ra, 184(t0)
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sll r0, r0, 0
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sll r0, r0, 0
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sll r0, r0, 0
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daddiu ra, ra, 1
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sll r0, r0, 0
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sw ra, 184(t0)
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beq r0, r0, L52
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sll r0, r0, 0
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B22:
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L53:
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sw a3, 128(t1) ;; kick off the next spr-from.
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xori a3, a3, 6144
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sw v1, 16(t1) ;; to the dma-buf
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|
|
sll ra, t6, 4
|
||
|
|
addu v1, v1, ra ;; add qwc
|
||
|
|
or ra, a3, r0 ;; ra is the spad-side dma buffer to write to
|
||
|
|
sw t6, 32(t1) ;; qwc
|
||
|
|
addiu t6, r0, 256
|
||
|
|
sw t6, 0(t1) ;; go!
|
||
|
|
addiu t6, r0, 0 ;; reset use.
|
||
|
|
|
||
|
|
;; actually building dma.
|
||
|
|
B23:
|
||
|
|
L54:
|
||
|
|
and gp, t7, t9 ;; vis check
|
||
|
|
vmulax.xyzw acc, vf16, vf2 ;; plane ?
|
||
|
|
beq gp, r0, L64_8loop_reject ;; vis check failed, reject!
|
||
|
|
lwu gp, 36(t8) ;; DMA BASE (chain) -------------
|
||
|
|
|
||
|
|
B24:
|
||
|
|
vmadday.xyzw acc, vf17, vf2 ;; plane
|
||
|
|
lbu s5, 45(t8) ;; DMA QWC1
|
||
|
|
vmaddaz.xyzw acc, vf18, vf2 ;; plane
|
||
|
|
sw gp, 4(t0) ;; base tmpl set addr
|
||
|
|
vmsubaw.xyzw acc, vf19, vf0 ;; plane
|
||
|
|
sh s5, 0(t0) ;; base tmpl set qwc
|
||
|
|
vmaddw.xyzw vf5, vf1, vf2 ;; plane
|
||
|
|
lwu gp, 32(t8) ;; DMA level0 -------------
|
||
|
|
vmulaw.xyzw acc, vf27, vf0 ;; camrot
|
||
|
|
lbu s5, 47(t8) ;; DMA QWC3
|
||
|
|
vmaddax.xyzw acc, vf24, vf2 ;; camrot
|
||
|
|
sw gp, 20(t0) ;; l0 tmpl set addr
|
||
|
|
vmadday.xyzw acc, vf25, vf2 ;; camrot
|
||
|
|
sh s5, 16(t0) ;; l0 tmpl set qwc
|
||
|
|
vmaddaz.xyzw acc, vf26, vf2 ;; camrot
|
||
|
|
lwu gp, 32(t8) ;; DMA common --------------
|
||
|
|
qmfc2.i s5, vf5 ;; plane
|
||
|
|
lbu s4, 44(t8) ;; DMA QWC0
|
||
|
|
vmaddw.xyzw vf6, vf1, vf2 ;; ??
|
||
|
|
sw gp, 36(t0) ;; common tmpl set addr
|
||
|
|
vmsubw.xyzw vf8, vf1, vf2 ;; ??
|
||
|
|
sh s4, 32(t0) ;; common tmpl set qwc
|
||
|
|
pcgtw s5, r0, s5 ;; plane check
|
||
|
|
lwu gp, 40(t8) ;; DMA level1 -------------
|
||
|
|
ppach s5, r0, s5 ;; plane check
|
||
|
|
lbu s4, 46(t8) ;; DMA QWC2
|
||
|
|
vaddz.xyzw vf6, vf3, vf6 ;; dist
|
||
|
|
sw gp, 52(t0) ;; l1 tmpl addr
|
||
|
|
vaddz.xyzw vf7, vf3, vf8 ;; dist
|
||
|
|
sw t3, 12(t0) ;; !!! set a vif on base, 0 on the first round, at least.
|
||
|
|
bne s5, r0, L63_8loop_reject_tog_vis
|
||
|
|
sh s4, 48(t0) ;; l1 tmpl qwc
|
||
|
|
|
||
|
|
B25:
|
||
|
|
vmini.xyzw vf4, vf4, vf8 ;; max dist
|
||
|
|
sw t3, 28(t0) ;; !!! set a vif on l0
|
||
|
|
sll r0, r0, 0
|
||
|
|
lbu s5, 53(t8) ;; s5 = num-base-colors
|
||
|
|
qmfc2.i gp, vf6 ;; dist
|
||
|
|
sw t3, 44(t0) ;; !!! set a vif on common
|
||
|
|
qmfc2.i s3, vf7 ;; dist
|
||
|
|
lbu s4, 56(t8) ;; s4 = color-offset
|
||
|
|
pcgtw s2, r0, gp ;; dist
|
||
|
|
lw gp, 12(t8) ;; gp = colors-indices
|
||
|
|
pcgtw s3, r0, s3 ;; dist
|
||
|
|
sb s4, 76(t0) ;; store color-offset
|
||
|
|
pinteh s4, s2, s3 ;; dist
|
||
|
|
lbu s2, 54(t8) ;; s2 = num-level0-colors
|
||
|
|
ppacb s3, r0, s4 ;; dist
|
||
|
|
lbu s1, 55(t8) ;; s1 = num-level1-colors
|
||
|
|
beq s3, r0, L56 ;; jump if dist fails?
|
||
|
|
dsrl32 s4, s3, 8 ;; s4 is the level or something?
|
||
|
|
|
||
|
|
B26:
|
||
|
|
beq s2, r0, L56 ;; if we have no level0 colors, use base
|
||
|
|
sll r0, r0, 0
|
||
|
|
|
||
|
|
B27:
|
||
|
|
beq s1, r0, L55 ;; if we have no level1 colors, use level0
|
||
|
|
dsrl s5, s3, 16
|
||
|
|
|
||
|
|
B28:
|
||
|
|
beq s5, r0, L55 ;; possible l1 skip based on lod
|
||
|
|
dsrl32 s5, s3, 24
|
||
|
|
|
||
|
|
B29:
|
||
|
|
bne s5, r0, L64_8loop_reject ;; possible all skip based on lod.
|
||
|
|
addiu s5, s1, 3 ;; s5 = num-level1-colors + 3
|
||
|
|
|
||
|
|
B30: ;; level 1 color setup
|
||
|
|
sra s4, s5, 2 ;; s4 = (num_color + 3) >> 4
|
||
|
|
or s5, s1, r0 ;; s5 = (num_color)
|
||
|
|
sll t3, s4, 2 ;; t3 = num colors, 4 aligned
|
||
|
|
sh s4, 64(t0) ;; color-tmpl qwc.
|
||
|
|
sll r0, r0, 0
|
||
|
|
sb t3, 78(t0) ;; vif store
|
||
|
|
daddiu t6, t6, 3 ;; use 3 qw's of global dma.
|
||
|
|
lq s2, 32(t0) ;; load the common-tmpl!
|
||
|
|
sll r0, r0, 0
|
||
|
|
lq s1, 48(t0) ;; load the l1 tmpl!
|
||
|
|
sll r0, r0, 0
|
||
|
|
lq t3, 64(t0) ;; load the color tmpl!
|
||
|
|
sq s2, 0(ra) ;; store the common!
|
||
|
|
sll r0, r0, 0
|
||
|
|
sq s1, 16(ra) ;; store the l1!
|
||
|
|
dsrl32 s2, s3, 16
|
||
|
|
sq t3, 32(ra) ;; store the color
|
||
|
|
daddiu ra, ra, 48 ;; advance the dma buffer pointer
|
||
|
|
bne s2, r0, L57
|
||
|
|
ori t3, t2, 18 ;; is this.. program 18?
|
||
|
|
|
||
|
|
B31:
|
||
|
|
dsrl32 t3, s3, 8
|
||
|
|
sll r0, r0, 0
|
||
|
|
bne t3, r0, L57
|
||
|
|
ori t3, t2, 16
|
||
|
|
|
||
|
|
B32:
|
||
|
|
beq r0, r0, L57
|
||
|
|
ori t3, t2, 14
|
||
|
|
|
||
|
|
B33:
|
||
|
|
L55:
|
||
|
|
bne s4, r0, L64_8loop_reject
|
||
|
|
addiu s5, s2, 3 ;; l0 colors + 3
|
||
|
|
|
||
|
|
B34: l0 color setup
|
||
|
|
sra s4, s5, 2 ;; >> 2
|
||
|
|
or s5, s2, r0 ;; s5 = qwc
|
||
|
|
sll t3, s4, 2 ;; << 2
|
||
|
|
sh s4, 64(t0) ;; color-tmpl qwc
|
||
|
|
sll r0, r0, 0
|
||
|
|
sb t3, 78(t0) ;; vif store for unpack??
|
||
|
|
daddiu t6, t6, 2 ;; only 2 qw's
|
||
|
|
lq s2, 16(t0) ;; l0 tmpl
|
||
|
|
sll r0, r0, 0
|
||
|
|
lq t3, 64(t0) ;; color tmp
|
||
|
|
sq s2, 0(ra)
|
||
|
|
dsrl s3, s3, 8
|
||
|
|
sq t3, 16(ra)
|
||
|
|
daddiu ra, ra, 32
|
||
|
|
bne s3, r0, L57
|
||
|
|
ori t3, t2, 10
|
||
|
|
|
||
|
|
B35:
|
||
|
|
beq r0, r0, L57
|
||
|
|
ori t3, t2, 8
|
||
|
|
|
||
|
|
B36:
|
||
|
|
L56:
|
||
|
|
bne s4, r0, L64_8loop_reject
|
||
|
|
addiu s4, s5, 3 ;; base colors + 3
|
||
|
|
|
||
|
|
B37:
|
||
|
|
sra s4, s4, 2
|
||
|
|
sll r0, r0, 0
|
||
|
|
sll t3, s4, 2
|
||
|
|
sh s4, 64(t0)
|
||
|
|
sll r0, r0, 0
|
||
|
|
sb t3, 78(t0)
|
||
|
|
ori t3, t2, 6
|
||
|
|
lq s3, 0(t0) ;; base
|
||
|
|
daddiu t6, t6, 2
|
||
|
|
lq s2, 64(t0) ;; color
|
||
|
|
sq s3, 0(ra)
|
||
|
|
sll r0, r0, 0
|
||
|
|
sq s2, 16(ra)
|
||
|
|
daddiu ra, ra, 32
|
||
|
|
|
||
|
|
;; END of the color setup
|
||
|
|
B38:
|
||
|
|
L57: ;; another opportunity to do some spad swappin
|
||
|
|
addiu s3, r0, 127 ;; s3 = 127
|
||
|
|
daddu s2, t6, s4 ;; s2 = dma-use + color qwc
|
||
|
|
dsubu s3, s3, s2
|
||
|
|
sll r0, r0, 0
|
||
|
|
bgez s3, L60
|
||
|
|
sll r0, r0, 0
|
||
|
|
|
||
|
|
B39:
|
||
|
|
L58:
|
||
|
|
lw ra, 0(t1)
|
||
|
|
sll r0, r0, 0
|
||
|
|
sll r0, r0, 0
|
||
|
|
sll r0, r0, 0
|
||
|
|
andi ra, ra, 256
|
||
|
|
sll r0, r0, 0
|
||
|
|
beq ra, r0, L59
|
||
|
|
sll r0, r0, 0
|
||
|
|
|
||
|
|
B40:
|
||
|
|
sll r0, r0, 0
|
||
|
|
lw ra, 184(t0)
|
||
|
|
sll r0, r0, 0
|
||
|
|
sll r0, r0, 0
|
||
|
|
sll r0, r0, 0
|
||
|
|
daddiu ra, ra, 1
|
||
|
|
sll r0, r0, 0
|
||
|
|
sw ra, 184(t0)
|
||
|
|
beq r0, r0, L58
|
||
|
|
sll r0, r0, 0
|
||
|
|
|
||
|
|
B41:
|
||
|
|
L59:
|
||
|
|
sw a3, 128(t1)
|
||
|
|
xori a3, a3, 6144
|
||
|
|
sw v1, 16(t1)
|
||
|
|
sll ra, t6, 4
|
||
|
|
addu v1, v1, ra
|
||
|
|
or ra, a3, r0
|
||
|
|
sw t6, 32(t1)
|
||
|
|
addiu t6, r0, 256
|
||
|
|
sw t6, 0(t1)
|
||
|
|
addiu t6, r0, 0
|
||
|
|
B42:
|
||
|
|
|
||
|
|
L60:
|
||
|
|
daddu t6, t6, s4 ;; add color imm's to dma buffer length
|
||
|
|
sw t8, 168(t0) ;; back up tfrag... not enough regs
|
||
|
|
ld s4, 0(gp) ;; load color-indices (u64 = u16 x 4)
|
||
|
|
daddiu t8, gp, 8 ;; inc colors ptr
|
||
|
|
daddiu gp, s5, -4 ;; gp is color counter. we're using the rounded up to 4 color count.
|
||
|
|
lq s5, 128(t0) ;; color-ptr x4
|
||
|
|
pextlh s4, r0, s4 ;; expand packed u16's to u32's
|
||
|
|
mfc1 r0, f31 ;; nop
|
||
|
|
paddw s2, s4, s5 ;; add to color pointers
|
||
|
|
mfc1 r0, f31
|
||
|
|
lw s4, 0(s2) ;; s4 = colors[0]
|
||
|
|
dsra32 s3, s2, 0
|
||
|
|
lw s3, 0(s3) ;; s5 = colors[1]
|
||
|
|
pcpyud s1, s2, s2
|
||
|
|
lw s2, 0(s1) ;; s2 = colors[2]
|
||
|
|
dsra32 s1, s1, 0
|
||
|
|
blez gp, L62
|
||
|
|
lw s1, 0(s1) ;; s1 = colors[3]
|
||
|
|
|
||
|
|
B43:
|
||
|
|
L61:
|
||
|
|
ld s0, 0(t8)
|
||
|
|
daddiu ra, ra, 16
|
||
|
|
daddiu t8, t8, 8
|
||
|
|
sw s4, -16(ra)
|
||
|
|
daddiu gp, gp, -4
|
||
|
|
sw s3, -12(ra)
|
||
|
|
pextlh s4, r0, s0
|
||
|
|
sw s2, -8(ra)
|
||
|
|
paddw s2, s4, s5
|
||
|
|
sw s1, -4(ra)
|
||
|
|
lw s4, 0(s2)
|
||
|
|
dsra32 s3, s2, 0
|
||
|
|
lw s3, 0(s3)
|
||
|
|
pcpyud s1, s2, s2
|
||
|
|
lw s2, 0(s1)
|
||
|
|
dsra32 s1, s1, 0
|
||
|
|
bgtz gp, L61
|
||
|
|
lw s1, 0(s1)
|
||
|
|
|
||
|
|
B44:
|
||
|
|
L62:
|
||
|
|
daddiu ra, ra, 16
|
||
|
|
lw t8, 168(t0)
|
||
|
|
sll r0, r0, 0
|
||
|
|
sw s4, -16(ra)
|
||
|
|
sll r0, r0, 0
|
||
|
|
sw s3, -12(ra)
|
||
|
|
sll r0, r0, 0
|
||
|
|
sw s2, -8(ra)
|
||
|
|
sll r0, r0, 0
|
||
|
|
sw s1, -4(ra)
|
||
|
|
B45:
|
||
|
|
L63_8loop_reject_tog_vis:
|
||
|
|
xor t7, t7, t9 ;; update vis
|
||
|
|
sll r0, r0, 0
|
||
|
|
B46:
|
||
|
|
L64_8loop_reject:
|
||
|
|
daddiu t8, t8, 64
|
||
|
|
srl t9, t9, 1
|
||
|
|
addiu a2, a2, -1
|
||
|
|
sll r0, r0, 0
|
||
|
|
bne t9, r0, L51
|
||
|
|
lqc2 vf2, 16(t8)
|
||
|
|
|
||
|
|
B47:
|
||
|
|
L65:
|
||
|
|
sll r0, r0, 0
|
||
|
|
lw gp, 160(t0)
|
||
|
|
sll r0, r0, 0
|
||
|
|
lw t9, 164(t0)
|
||
|
|
bne gp, t9, L49
|
||
|
|
sb t7, -1(gp)
|
||
|
|
|
||
|
|
B48:
|
||
|
|
bgtz a2, L43_MAIN_LOOP_TOP
|
||
|
|
sll r0, r0, 0
|
||
|
|
|
||
|
|
B49:
|
||
|
|
beq t6, r0, L68
|
||
|
|
sll r0, r0, 0
|
||
|
|
|
||
|
|
B50:
|
||
|
|
L66:
|
||
|
|
lw a0, 0(t1)
|
||
|
|
sll r0, r0, 0
|
||
|
|
sll r0, r0, 0
|
||
|
|
sll r0, r0, 0
|
||
|
|
andi a0, a0, 256
|
||
|
|
sll r0, r0, 0
|
||
|
|
beq a0, r0, L67
|
||
|
|
sll r0, r0, 0
|
||
|
|
|
||
|
|
B51:
|
||
|
|
sll r0, r0, 0
|
||
|
|
lw a0, 184(t0)
|
||
|
|
sll r0, r0, 0
|
||
|
|
sll r0, r0, 0
|
||
|
|
sll r0, r0, 0
|
||
|
|
daddiu a0, a0, 1
|
||
|
|
sll r0, r0, 0
|
||
|
|
sw a0, 184(t0)
|
||
|
|
beq r0, r0, L66
|
||
|
|
sll r0, r0, 0
|
||
|
|
|
||
|
|
B52:
|
||
|
|
L67:
|
||
|
|
sw a3, 128(t1)
|
||
|
|
xori a0, a3, 6144
|
||
|
|
sw v1, 16(t1)
|
||
|
|
sll a1, t6, 4
|
||
|
|
addu v1, v1, a1
|
||
|
|
or a0, a0, r0
|
||
|
|
sw t6, 32(t1)
|
||
|
|
addiu a0, r0, 256
|
||
|
|
sw a0, 0(t1)
|
||
|
|
addiu a0, r0, 0
|
||
|
|
B53:
|
||
|
|
L68:
|
||
|
|
lw a0, 0(t1)
|
||
|
|
sll r0, r0, 0
|
||
|
|
sll r0, r0, 0
|
||
|
|
sll r0, r0, 0
|
||
|
|
andi a0, a0, 256
|
||
|
|
sll r0, r0, 0
|
||
|
|
beq a0, r0, L69_CLEANUP
|
||
|
|
sll r0, r0, 0
|
||
|
|
|
||
|
|
B54:
|
||
|
|
sll r0, r0, 0
|
||
|
|
lw a0, 184(t0)
|
||
|
|
sll r0, r0, 0
|
||
|
|
sll r0, r0, 0
|
||
|
|
sll r0, r0, 0
|
||
|
|
daddiu a0, a0, 1
|
||
|
|
sll r0, r0, 0
|
||
|
|
sw a0, 184(t0)
|
||
|
|
beq r0, r0, L68
|
||
|
|
sll r0, r0, 0
|
||
|
|
|
||
|
|
B55:
|
||
|
|
L69_CLEANUP:
|
||
|
|
lw a0, 176(t0)
|
||
|
|
sll r0, r0, 0
|
||
|
|
sw t3, 172(t0)
|
||
|
|
sll r0, r0, 0
|
||
|
|
sqc2 vf4, 112(t0)
|
||
|
|
sll r0, r0, 0
|
||
|
|
sw v1, 4(a0)
|
||
|
|
sll r0, r0, 0
|
||
|
|
or v0, r0, r0
|
||
|
|
ld ra, 0(sp)
|
||
|
|
lq gp, 112(sp)
|
||
|
|
lq s5, 96(sp)
|
||
|
|
lq s4, 80(sp)
|
||
|
|
lq s3, 64(sp)
|
||
|
|
lq s2, 48(sp)
|
||
|
|
lq s1, 32(sp)
|
||
|
|
lq s0, 16(sp)
|
||
|
|
jr ra
|
||
|
|
daddiu sp, sp, 128
|
||
|
|
|
||
|
|
sll r0, r0, 0
|
||
|
|
sll r0, r0, 0
|
||
|
|
sll r0, r0, 0
|
||
|
|
|
||
|
|
|
||
|
|
Notes on the VU program
|
||
|
|
vi03 is a pointer to an "address book" - a sequence of addresses
|
||
|
|
vi02 contains addresses in this book
|
||
|
|
from these xyw are loaded for vf28 (v3-32, with 2, 1)
|
||
|
|
xy are floats. w is address of next vertex data.
|
||
|
|
|
||
|
|
vi08 is a pointer to adgifs?
|
||
|
|
vi09 is a pointer to some data like [vi12, ?, ?, vi13] ??
|
||
|
|
|
||
|
|
vi12 counter, started negative?
|
||
|
|
vi13 is adgif offset?
|
||
|
|
|
||
|
|
vi04 is a pointer to tri-data:
|
||
|
|
- vertex (w = 128.0?)
|
||
|
|
- ?? (vf20)
|